diff options
| author | Eric Anholt <[email protected]> | 2016-07-19 11:10:36 -0700 |
|---|---|---|
| committer | Eric Anholt <[email protected]> | 2016-07-26 13:47:50 -0700 |
| commit | ce8504d196291452b42ed755ed3830ecb16febcd (patch) | |
| tree | c9e4b018baa6c1ab1df2b82e71f54db4ba5c1790 /src/gallium/drivers/vc4/vc4_emit.c | |
| parent | 4d0b2c7aaac3cf3de5af8474c83501122841d157 (diff) | |
vc4: Disable early Z with computed depth.
We don't tell the hardware whether we're computing depth, so we need
to manage early Z state manually. Fixes piglit early-z.
Diffstat (limited to 'src/gallium/drivers/vc4/vc4_emit.c')
| -rw-r--r-- | src/gallium/drivers/vc4/vc4_emit.c | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/src/gallium/drivers/vc4/vc4_emit.c b/src/gallium/drivers/vc4/vc4_emit.c index 5d647977755..8b192da47f2 100644 --- a/src/gallium/drivers/vc4/vc4_emit.c +++ b/src/gallium/drivers/vc4/vc4_emit.c @@ -71,7 +71,9 @@ vc4_emit_state(struct pipe_context *pctx) vc4->draw_max_y = MAX2(vc4->draw_max_y, maxy); } - if (vc4->dirty & (VC4_DIRTY_RASTERIZER | VC4_DIRTY_ZSA)) { + if (vc4->dirty & (VC4_DIRTY_RASTERIZER | + VC4_DIRTY_ZSA | + VC4_DIRTY_COMPILED_FS)) { uint8_t ez_enable_mask_out = ~0; /* HW-2905: If the RCL ends up doing a full-res load when @@ -83,7 +85,7 @@ vc4_emit_state(struct pipe_context *pctx) * was seeing bad rendering on glxgears -samples 4 even in * that case. */ - if (vc4->msaa) + if (vc4->msaa || vc4->prog.fs->disable_early_z) ez_enable_mask_out &= ~VC4_CONFIG_BITS_EARLY_Z; cl_u8(&bcl, VC4_PACKET_CONFIGURATION_BITS); |