broadcom/vc4: Expose PIPE_CAP_TILE_RASTER_ORDER

Because vc4 can control the order that tiles are rasterized in, we can use
it to implement overlapping blits using normal drawing and
GL_ARB_texture_barrier, as long as we can tell the kernel what order to
render the tiles in.

v2: Fix on the simulator.
v3: Add the cap (disabled) to other drivers, add rst docs for the cap.
v4: Rebase on PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS
v5: Split from the core gallium commit, drop some unnecessary code related
    to glBlitFramebuffer(), fix a crash with clears before state has been
    bound.

1 files changed, 6 insertions, 0 deletions

diff --git a/src/gallium/drivers/vc4/vc4_context.h b/src/gallium/drivers/vc4/vc4_context.h
index 99ec7e5d2e8..4a1e4093f1a 100644
--- a/src/gallium/drivers/vc4/vc4_context.h
+++ b/src/gallium/drivers/vc4/vc4_context.h
@@ -303,6 +303,9 @@ struct vc4_job {
          */
         uint32_t draw_calls_queued;
 
+        /** Any flags to be passed in drm_vc4_submit_cl.flags. */
+        uint32_t flags;
+
         struct vc4_job_key key;
 };
 
@@ -398,6 +401,9 @@ struct vc4_rasterizer_state {
                 uint8_t point_size[V3D21_POINT_SIZE_length];
                 uint8_t line_width[V3D21_LINE_WIDTH_length];
         } packed;
+
+        /** Raster order flags to be passed in struct drm_vc4_submit_cl.flags. */
+        uint32_t tile_raster_order_flags;
 };
 
 struct vc4_depth_stencil_alpha_state {