diff options
| author | Eric Anholt <[email protected]> | 2015-06-11 16:08:11 -0700 |
|---|---|---|
| committer | Eric Anholt <[email protected]> | 2015-06-16 15:15:14 -0700 |
| commit | 731ac05cc4e444175288032a76a29c95059af038 (patch) | |
| tree | adfcfe0b57843f52d31ad63267f812cc1a0d5283 /src/gallium/drivers/vc4/vc4_blit.c | |
| parent | e22a1927844cdda499ea15f539028c16e47394ea (diff) | |
vc4: Use VC4_SET/GET_FIELD for some RCL packets.
Diffstat (limited to 'src/gallium/drivers/vc4/vc4_blit.c')
| -rw-r--r-- | src/gallium/drivers/vc4/vc4_blit.c | 29 |
1 files changed, 16 insertions, 13 deletions
diff --git a/src/gallium/drivers/vc4/vc4_blit.c b/src/gallium/drivers/vc4/vc4_blit.c index 58066501428..b3811025cc1 100644 --- a/src/gallium/drivers/vc4/vc4_blit.c +++ b/src/gallium/drivers/vc4/vc4_blit.c @@ -54,11 +54,13 @@ vc4_tile_blit_color_rcl(struct vc4_context *vc4, cl_reloc(vc4, &vc4->rcl, dst->bo, dst_surf->offset); cl_u16(&vc4->rcl, dst_surf->base.width); cl_u16(&vc4->rcl, dst_surf->base.height); - cl_u16(&vc4->rcl, ((dst_surf->tiling << - VC4_RENDER_CONFIG_MEMORY_FORMAT_SHIFT) | - (vc4_rt_format_is_565(dst_surf->base.format) ? - VC4_RENDER_CONFIG_FORMAT_BGR565 : - VC4_RENDER_CONFIG_FORMAT_RGBA8888))); + cl_u16(&vc4->rcl, + VC4_SET_FIELD(dst_surf->tiling, + VC4_RENDER_CONFIG_MEMORY_FORMAT) | + VC4_SET_FIELD(vc4_rt_format_is_565(dst_surf->base.format) ? + VC4_RENDER_CONFIG_FORMAT_BGR565 : + VC4_RENDER_CONFIG_FORMAT_RGBA8888, + VC4_RENDER_CONFIG_FORMAT)); uint32_t src_hindex = vc4_gem_hindex(vc4, src->bo); @@ -69,14 +71,15 @@ vc4_tile_blit_color_rcl(struct vc4_context *vc4, cl_start_reloc(&vc4->rcl, 1); cl_u8(&vc4->rcl, VC4_PACKET_LOAD_TILE_BUFFER_GENERAL); - cl_u8(&vc4->rcl, - VC4_LOADSTORE_TILE_BUFFER_COLOR | - (src_surf->tiling << - VC4_LOADSTORE_TILE_BUFFER_FORMAT_SHIFT)); - cl_u8(&vc4->rcl, - vc4_rt_format_is_565(src_surf->base.format) ? - VC4_LOADSTORE_TILE_BUFFER_BGR565 : - VC4_LOADSTORE_TILE_BUFFER_RGBA8888); + cl_u16(&vc4->rcl, + VC4_SET_FIELD(VC4_LOADSTORE_TILE_BUFFER_COLOR, + VC4_LOADSTORE_TILE_BUFFER_BUFFER) | + VC4_SET_FIELD(src_surf->tiling, + VC4_LOADSTORE_TILE_BUFFER_TILING) | + VC4_SET_FIELD(vc4_rt_format_is_565(src_surf->base.format) ? + VC4_LOADSTORE_TILE_BUFFER_BGR565 : + VC4_LOADSTORE_TILE_BUFFER_RGBA8888, + VC4_LOADSTORE_TILE_BUFFER_FORMAT)); cl_reloc_hindex(&vc4->rcl, src_hindex, src_surf->offset); |