summaryrefslogtreecommitdiffstats
path: root/src/gallium/drivers/tegra
diff options
context:
space:
mode:
authorKenneth Graunke <[email protected]>2019-03-05 20:43:11 -0800
committerKenneth Graunke <[email protected]>2019-03-19 23:43:33 -0700
commit220c1dce1e3194ea867e6d948fc7ff5b9ef2d3a7 (patch)
tree14c37a6bf22d367e6338d26a1529bb8c73322bcb /src/gallium/drivers/tegra
parent3e534489ecb0d4e042a14ac344d54b425a03848b (diff)
gallium: Add PIPE_BARRIER_UPDATE_BUFFER and UPDATE_TEXTURE bits.
The glMemoryBarrier() function makes shader memory stores ordered with respect to things specified by the given bits. Until now, st/mesa has ignored GL_TEXTURE_UPDATE_BARRIER_BIT and GL_BUFFER_UPDATE_BARRIER_BIT, saying that drivers should implicitly perform the needed flushing. This seems like a pretty big assumption to make. Instead, this commit opts to translate them to new PIPE_BARRIER bits, and adjusts existing drivers to continue ignoring them (preserving the current behavior). The i965 driver performs actions on these memory barriers. Shader memory stores go through a "data cache" which is separate from the render cache and other read caches (like the texture cache). All memory barriers need to flush the data cache (to ensure shader memory stores are visible), and possibly invalidate read caches (to ensure stale data is no longer visible). The driver implicitly flushes for most caches, but not for data cache, since ARB_shader_image_load_store introduced MemoryBarrier() precisely to order these explicitly. I would like to follow i965's approach in iris, flushing the data cache on any MemoryBarrier() call, so I need st/mesa to actually call the pipe->memory_barrier() callback. Fixes KHR-GL45.shader_image_load_store.advanced-sync-textureUpdate and Piglit's spec/arb_shader_image_load_store/host-mem-barrier on the iris driver. Roland said this looks reasonable to him. Reviewed-by: Eric Anholt <[email protected]>
Diffstat (limited to 'src/gallium/drivers/tegra')
-rw-r--r--src/gallium/drivers/tegra/tegra_context.c3
1 files changed, 3 insertions, 0 deletions
diff --git a/src/gallium/drivers/tegra/tegra_context.c b/src/gallium/drivers/tegra/tegra_context.c
index bbc03628336..e9e51656921 100644
--- a/src/gallium/drivers/tegra/tegra_context.c
+++ b/src/gallium/drivers/tegra/tegra_context.c
@@ -974,6 +974,9 @@ tegra_memory_barrier(struct pipe_context *pcontext, unsigned int flags)
{
struct tegra_context *context = to_tegra_context(pcontext);
+ if (!(flags & ~PIPE_BARRIER_UPDATE))
+ return;
+
context->gpu->memory_barrier(context->gpu, flags);
}