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author | Ben Widawsky <[email protected]> | 2017-05-01 10:07:47 -0700 |
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committer | Anuj Phogat <[email protected]> | 2017-06-20 12:18:26 -0700 |
commit | 3e1055591b442ed367d9f6b80c8912f0cae94b95 (patch) | |
tree | 870bb7a3100e21eb66c903e9ec61ba815633fbb5 /src/gallium/drivers/swr/swr_state.cpp | |
parent | 1024dad4d936b6a618e58522071c37a0989832f1 (diff) |
i965/cnl: Add l3 configuration for Cannonlake
V2 (Anuj):
Squash the changes in one patch rebase on master.
Address the review comments made by Francisco Jerez.
Do the URB allocation per slice (not per bank).
V3 (Anuj):
Update the comment.
Format the table as other l3 config tables.
Signed-off-by: Ben Widawsky <[email protected]>
Signed-off-by: Anuj Phogat <[email protected]>
Reviewed-by: Francisco Jerez <[email protected]>
---
V1 was sent out with the heading:
"i965/cnl: Properly handle l3 configuration"
Diffstat (limited to 'src/gallium/drivers/swr/swr_state.cpp')
0 files changed, 0 insertions, 0 deletions