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authorBrian Paul <brianp@vmware.com>2017-07-11 14:56:00 -0600
committerBrian Paul <brianp@vmware.com>2017-07-11 15:43:36 -0600
commitf7e78abdf45b26f3991dc336120162ae01b208f1 (patch)
tree644c680046d1fe7381ded57a8a98c3e3e26c794f /src/gallium/drivers/svga
parentcead51a0c63df1613f9f6400657597679126024c (diff)
svga: fix texture swizzle writemasking
Commit bfe1e7737a76e3b046 changed how texture swizzles are set up. This exposed a latent bug in the VMware driver: we were ignoring the texture instruction's writemask when applying the 0 and 1 swizzle terms. This wasn't caught by the Piglit texture swizzle test because it only exercises fixed function (no write masking). Fixes issues seen with ETQW apitrace. CC: <mesa-stable@lists.freedesktop.org> Reviewed-by: Charmaine Lee <charmainel@vmware.com>
Diffstat (limited to 'src/gallium/drivers/svga')
-rw-r--r--src/gallium/drivers/svga/svga_tgsi_vgpu10.c2
1 files changed, 2 insertions, 0 deletions
diff --git a/src/gallium/drivers/svga/svga_tgsi_vgpu10.c b/src/gallium/drivers/svga/svga_tgsi_vgpu10.c
index d29ac282405..96269cb872b 100644
--- a/src/gallium/drivers/svga/svga_tgsi_vgpu10.c
+++ b/src/gallium/drivers/svga/svga_tgsi_vgpu10.c
@@ -5047,6 +5047,7 @@ end_tex_swizzle(struct svga_shader_emitter_v10 *emit,
((swz_g == PIPE_SWIZZLE_0) << 1) |
((swz_b == PIPE_SWIZZLE_0) << 2) |
((swz_a == PIPE_SWIZZLE_0) << 3));
+ writemask_0 &= swz->inst_dst->Register.WriteMask;
if (writemask_0) {
struct tgsi_full_src_register zero = int_tex ?
@@ -5065,6 +5066,7 @@ end_tex_swizzle(struct svga_shader_emitter_v10 *emit,
((swz_g == PIPE_SWIZZLE_1) << 1) |
((swz_b == PIPE_SWIZZLE_1) << 2) |
((swz_a == PIPE_SWIZZLE_1) << 3));
+ writemask_1 &= swz->inst_dst->Register.WriteMask;
if (writemask_1) {
struct tgsi_full_src_register one = int_tex ?