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authorLionel Landwerlin <[email protected]>2020-01-15 14:06:07 +0200
committerMarge Bot <[email protected]>2020-02-05 00:25:48 +0000
commit19e7bcee1742a40981a0b1c06447bca22646c294 (patch)
tree05f8872902569e1ee04308bcd2b2b271c972e2d4 /src/gallium/drivers/svga/svga_pipe_draw.c
parent2c07e03b792d57ae807a6953f0d8ff5f4bcdffd0 (diff)
iris: implement gen12 post sync pipe control workaround
Like Skylake, Gen12 requires a workaround for PIPE_CONTROLs using a post-sync operation. v2: Restrict to A0 Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3405>
Diffstat (limited to 'src/gallium/drivers/svga/svga_pipe_draw.c')
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