gallium/radeon: don't allocate HTILE in a separate buffer

Reviewed-by: Samuel Pitoiset <[email protected]>
Reviewed-by: Nicolai Hähnle <[email protected]>

3 files changed, 8 insertions, 19 deletions

diff --git a/src/gallium/drivers/radeonsi/si_blit.c b/src/gallium/drivers/radeonsi/si_blit.c
index e39ba62e0b8..74bc2e9a51a 100644
--- a/src/gallium/drivers/radeonsi/si_blit.c
+++ b/src/gallium/drivers/radeonsi/si_blit.c
@@ -726,7 +726,7 @@ static void si_clear(struct pipe_context *ctx, unsigned buffers,
 		}
 	}
 
-	if (zstex && zstex->htile_buffer &&
+	if (zstex && zstex->htile_offset &&
 	    zsbuf->u.tex.level == 0 &&
 	    zsbuf->u.tex.first_layer == 0 &&
 	    zsbuf->u.tex.last_layer == util_max_layer(&zstex->resource.b.b, 0)) {
diff --git a/src/gallium/drivers/radeonsi/si_descriptors.c b/src/gallium/drivers/radeonsi/si_descriptors.c
index 3aa2b9d3fb1..0e8606f2bb3 100644
--- a/src/gallium/drivers/radeonsi/si_descriptors.c
+++ b/src/gallium/drivers/radeonsi/si_descriptors.c
@@ -337,13 +337,6 @@ static void si_sampler_view_add_buffer(struct si_context *sctx,
 						    rtex->dcc_separate_buffer, usage,
 						    RADEON_PRIO_DCC, check_mem);
 	}
-
-	if (rtex->htile_buffer &&
-	    rtex->tc_compatible_htile) {
-		radeon_add_to_buffer_list_check_mem(&sctx->b, &sctx->b.gfx,
-						    rtex->htile_buffer, usage,
-						    RADEON_PRIO_HTILE, check_mem);
-	}
 }
 
 static void si_sampler_views_begin_new_cs(struct si_context *sctx,
@@ -424,7 +417,7 @@ void si_set_mutable_tex_desc_fields(struct si_screen *sscreen,
 			if (sscreen->b.chip_class <= VI)
 				meta_va += base_level_info->dcc_offset;
 		} else if (tex->tc_compatible_htile) {
-			meta_va = tex->htile_buffer->gpu_address;
+			meta_va = tex->resource.gpu_address + tex->htile_offset;
 		}
 
 		if (meta_va) {
diff --git a/src/gallium/drivers/radeonsi/si_state.c b/src/gallium/drivers/radeonsi/si_state.c
index c7bc7b0a9ca..53f66ac473e 100644
--- a/src/gallium/drivers/radeonsi/si_state.c
+++ b/src/gallium/drivers/radeonsi/si_state.c
@@ -2316,7 +2316,7 @@ static void si_init_depth_surface(struct si_context *sctx,
 				      S_02801C_Y_MAX(rtex->resource.b.b.height0 - 1);
 
 		/* Only use HTILE for the first level. */
-		if (rtex->htile_buffer && !level) {
+		if (rtex->htile_offset && !level) {
 			z_info |= S_028038_TILE_SURFACE_ENABLE(1) |
 				  S_028038_ALLOW_EXPCLEAR(1);
 
@@ -2342,7 +2342,8 @@ static void si_init_depth_surface(struct si_context *sctx,
 				s_info |= S_02803C_TILE_STENCIL_DISABLE(1);
 			}
 
-			surf->db_htile_data_base = rtex->htile_buffer->gpu_address >> 8;
+			surf->db_htile_data_base = (rtex->resource.gpu_address +
+						    rtex->htile_offset) >> 8;
 			surf->db_htile_surface = S_028ABC_FULL_CACHE(1) |
 						 S_028ABC_PIPE_ALIGNED(rtex->surface.u.gfx9.htile.pipe_aligned) |
 						 S_028ABC_RB_ALIGNED(rtex->surface.u.gfx9.htile.rb_aligned);
@@ -2394,7 +2395,7 @@ static void si_init_depth_surface(struct si_context *sctx,
 								levelinfo->nblk_y) / 64 - 1);
 
 		/* Only use HTILE for the first level. */
-		if (rtex->htile_buffer && !level) {
+		if (rtex->htile_offset && !level) {
 			z_info |= S_028040_TILE_SURFACE_ENABLE(1) |
 				  S_028040_ALLOW_EXPCLEAR(1);
 
@@ -2420,7 +2421,8 @@ static void si_init_depth_surface(struct si_context *sctx,
 				s_info |= S_028044_TILE_STENCIL_DISABLE(1);
 			}
 
-			surf->db_htile_data_base = rtex->htile_buffer->gpu_address >> 8;
+			surf->db_htile_data_base = (rtex->resource.gpu_address +
+						    rtex->htile_offset) >> 8;
 			surf->db_htile_surface = S_028ABC_FULL_CACHE(1);
 
 			if (rtex->tc_compatible_htile) {
@@ -2815,12 +2817,6 @@ static void si_emit_framebuffer_state(struct si_context *sctx, struct r600_atom
 					      RADEON_PRIO_DEPTH_BUFFER_MSAA :
 					      RADEON_PRIO_DEPTH_BUFFER);
 
-		if (zb->db_htile_data_base) {
-			radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
-					      rtex->htile_buffer, RADEON_USAGE_READWRITE,
-					      RADEON_PRIO_HTILE);
-		}
-
 		if (sctx->b.chip_class >= GFX9) {
 			radeon_set_context_reg_seq(cs, R_028014_DB_HTILE_DATA_BASE, 3);
 			radeon_emit(cs, zb->db_htile_data_base);	/* DB_HTILE_DATA_BASE */