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authorMarek Olšák <[email protected]>2017-11-28 17:54:55 +0100
committerMarek Olšák <[email protected]>2017-11-29 18:21:30 +0100
commit2c5f2936af642d8e4510154395215915c46b3fbb (patch)
tree9fddf92140a96e748e6af3b0f5fe691bf4ef7f1d /src/gallium/drivers/radeonsi
parent950221f9231eac6e76addf5e806e45fde6e35fc0 (diff)
r300,r600,radeonsi: replace RADEON_FLUSH_* with PIPE_FLUSH_*
and handle PIPE_FLUSH_HINT_FINISH in r300. Reviewed-by: Nicolai Hähnle <[email protected]>
Diffstat (limited to 'src/gallium/drivers/radeonsi')
-rw-r--r--src/gallium/drivers/radeonsi/si_fence.c6
-rw-r--r--src/gallium/drivers/radeonsi/si_hw_context.c6
-rw-r--r--src/gallium/drivers/radeonsi/si_state_shaders.c4
3 files changed, 8 insertions, 8 deletions
diff --git a/src/gallium/drivers/radeonsi/si_fence.c b/src/gallium/drivers/radeonsi/si_fence.c
index 5f478afaf63..0d165a14b54 100644
--- a/src/gallium/drivers/radeonsi/si_fence.c
+++ b/src/gallium/drivers/radeonsi/si_fence.c
@@ -271,7 +271,7 @@ static boolean si_fence_finish(struct pipe_screen *screen,
* not going to wait.
*/
threaded_context_unwrap_sync(ctx);
- sctx->b.gfx.flush(&sctx->b, timeout ? 0 : RADEON_FLUSH_ASYNC, NULL);
+ sctx->b.gfx.flush(&sctx->b, timeout ? 0 : PIPE_FLUSH_ASYNC, NULL);
rfence->gfx_unflushed.ctx = NULL;
if (!timeout)
@@ -378,10 +378,10 @@ static void si_flush_from_st(struct pipe_context *ctx,
struct pipe_fence_handle *sdma_fence = NULL;
bool deferred_fence = false;
struct si_fine_fence fine = {};
- unsigned rflags = RADEON_FLUSH_ASYNC;
+ unsigned rflags = PIPE_FLUSH_ASYNC;
if (flags & PIPE_FLUSH_END_OF_FRAME)
- rflags |= RADEON_FLUSH_END_OF_FRAME;
+ rflags |= PIPE_FLUSH_END_OF_FRAME;
if (flags & (PIPE_FLUSH_TOP_OF_PIPE | PIPE_FLUSH_BOTTOM_OF_PIPE)) {
assert(flags & PIPE_FLUSH_DEFERRED);
diff --git a/src/gallium/drivers/radeonsi/si_hw_context.c b/src/gallium/drivers/radeonsi/si_hw_context.c
index d46c1093f24..3823be056f3 100644
--- a/src/gallium/drivers/radeonsi/si_hw_context.c
+++ b/src/gallium/drivers/radeonsi/si_hw_context.c
@@ -53,7 +53,7 @@ void si_need_cs_space(struct si_context *ctx)
ctx->b.vram, ctx->b.gtt))) {
ctx->b.gtt = 0;
ctx->b.vram = 0;
- ctx->b.gfx.flush(ctx, RADEON_FLUSH_ASYNC, NULL);
+ ctx->b.gfx.flush(ctx, PIPE_FLUSH_ASYNC, NULL);
return;
}
ctx->b.gtt = 0;
@@ -63,7 +63,7 @@ void si_need_cs_space(struct si_context *ctx)
* and just flush if there is not enough space left.
*/
if (!ctx->b.ws->cs_check_space(cs, 2048))
- ctx->b.gfx.flush(ctx, RADEON_FLUSH_ASYNC, NULL);
+ ctx->b.gfx.flush(ctx, PIPE_FLUSH_ASYNC, NULL);
}
void si_context_gfx_flush(void *context, unsigned flags,
@@ -83,7 +83,7 @@ void si_context_gfx_flush(void *context, unsigned flags,
return;
if (ctx->screen->debug_flags & DBG(CHECK_VM))
- flags &= ~RADEON_FLUSH_ASYNC;
+ flags &= ~PIPE_FLUSH_ASYNC;
/* If the state tracker is flushing the GFX IB, r600_flush_from_st is
* responsible for flushing the DMA IB and merging the fences from both.
diff --git a/src/gallium/drivers/radeonsi/si_state_shaders.c b/src/gallium/drivers/radeonsi/si_state_shaders.c
index 461760f580d..4f683b85144 100644
--- a/src/gallium/drivers/radeonsi/si_state_shaders.c
+++ b/src/gallium/drivers/radeonsi/si_state_shaders.c
@@ -2822,7 +2822,7 @@ static bool si_update_gs_ring_buffers(struct si_context *sctx)
/* Flush the context to re-emit both init_config states. */
sctx->b.initial_gfx_cs_size = 0; /* force flush */
- si_context_gfx_flush(sctx, RADEON_FLUSH_ASYNC, NULL);
+ si_context_gfx_flush(sctx, PIPE_FLUSH_ASYNC, NULL);
/* Set ring bindings. */
if (sctx->esgs_ring) {
@@ -3161,7 +3161,7 @@ static void si_init_tess_factor_ring(struct si_context *sctx)
*/
si_pm4_upload_indirect_buffer(sctx, sctx->init_config);
sctx->b.initial_gfx_cs_size = 0; /* force flush */
- si_context_gfx_flush(sctx, RADEON_FLUSH_ASYNC, NULL);
+ si_context_gfx_flush(sctx, PIPE_FLUSH_ASYNC, NULL);
}
/**