gallium/radeon: add helpers for whether HTILE is enabled

Reviewed-by: Nicolai Hähnle <[email protected]>

3 files changed, 11 insertions, 12 deletions

diff --git a/src/gallium/drivers/radeonsi/si_blit.c b/src/gallium/drivers/radeonsi/si_blit.c
index 4e3b707b6cf..8add28f2060 100644
--- a/src/gallium/drivers/radeonsi/si_blit.c
+++ b/src/gallium/drivers/radeonsi/si_blit.c
@@ -381,7 +381,9 @@ si_decompress_depth(struct si_context *sctx,
 	}
 
 	if (inplace_planes) {
-		if (!tex->tc_compatible_htile) {
+		bool tc_compat_htile = vi_tc_compat_htile_enabled(tex, first_level);
+
+		if (!tc_compat_htile) {
 			si_blit_decompress_zs_in_place(
 						sctx, tex,
 						levels_z, levels_s,
@@ -393,10 +395,9 @@ si_decompress_depth(struct si_context *sctx,
 		 */
 		si_make_DB_shader_coherent(sctx, tex->resource.b.b.nr_samples,
 					   inplace_planes & PIPE_MASK_S,
-					   tex->tc_compatible_htile &&
-					   first_level == 0);
+					   tc_compat_htile);
 
-		if (tex->tc_compatible_htile) {
+		if (tc_compat_htile) {
 			/* Only clear the mask that we are flushing, because
 			 * si_make_DB_shader_coherent() can treat depth and
 			 * stencil differently.
@@ -859,8 +860,8 @@ static void si_clear(struct pipe_context *ctx, unsigned buffers,
 		}
 	}
 
-	if (zstex && zstex->htile_offset &&
-	    zsbuf->u.tex.level == 0 &&
+	if (zstex &&
+	    r600_htile_enabled(zstex, zsbuf->u.tex.level) &&
 	    zsbuf->u.tex.first_layer == 0 &&
 	    zsbuf->u.tex.last_layer == util_max_layer(&zstex->resource.b.b, 0)) {
 		/* TC-compatible HTILE only supports depth clears to 0 or 1. */
diff --git a/src/gallium/drivers/radeonsi/si_descriptors.c b/src/gallium/drivers/radeonsi/si_descriptors.c
index 646a9ec2570..446c52e7478 100644
--- a/src/gallium/drivers/radeonsi/si_descriptors.c
+++ b/src/gallium/drivers/radeonsi/si_descriptors.c
@@ -330,7 +330,7 @@ void si_set_mutable_tex_desc_fields(struct si_screen *sscreen,
 			}
 
 			meta_va |= (uint32_t)tex->surface.tile_swizzle << 8;
-		} else if (tex->tc_compatible_htile && first_level == 0) {
+		} else if (vi_tc_compat_htile_enabled(tex, first_level)) {
 			meta_va = tex->resource.gpu_address + tex->htile_offset;
 		}
 
diff --git a/src/gallium/drivers/radeonsi/si_state.c b/src/gallium/drivers/radeonsi/si_state.c
index d391d5f501a..cdcac0742c7 100644
--- a/src/gallium/drivers/radeonsi/si_state.c
+++ b/src/gallium/drivers/radeonsi/si_state.c
@@ -2327,8 +2327,7 @@ static void si_init_depth_surface(struct si_context *sctx,
 		surf->db_depth_size = S_02801C_X_MAX(rtex->resource.b.b.width0 - 1) |
 				      S_02801C_Y_MAX(rtex->resource.b.b.height0 - 1);
 
-		/* Only use HTILE for the first level. */
-		if (rtex->htile_offset && !level) {
+		if (r600_htile_enabled(rtex, level)) {
 			z_info |= S_028038_TILE_SURFACE_ENABLE(1) |
 				  S_028038_ALLOW_EXPCLEAR(1);
 
@@ -2406,8 +2405,7 @@ static void si_init_depth_surface(struct si_context *sctx,
 		surf->db_depth_slice = S_02805C_SLICE_TILE_MAX((levelinfo->nblk_x *
 								levelinfo->nblk_y) / 64 - 1);
 
-		/* Only use HTILE for the first level. */
-		if (rtex->htile_offset && !level) {
+		if (r600_htile_enabled(rtex, level)) {
 			z_info |= S_028040_TILE_SURFACE_ENABLE(1) |
 				  S_028040_ALLOW_EXPCLEAR(1);
 
@@ -2668,7 +2666,7 @@ static void si_set_framebuffer_state(struct pipe_context *ctx,
 			si_init_depth_surface(sctx, surf);
 		}
 
-		if (rtex->tc_compatible_htile && !surf->base.u.tex.level)
+		if (vi_tc_compat_htile_enabled(rtex, surf->base.u.tex.level))
 			sctx->framebuffer.DB_has_shader_readable_metadata = true;
 
 		r600_context_add_resource_size(ctx, surf->base.texture);