r600g,radeonsi: set priorities for relocations

7 files changed, 76 insertions, 35 deletions

diff --git a/src/gallium/drivers/radeonsi/si_compute.c b/src/gallium/drivers/radeonsi/si_compute.c
index ead5862df39..e16feab5234 100644
--- a/src/gallium/drivers/radeonsi/si_compute.c
+++ b/src/gallium/drivers/radeonsi/si_compute.c
@@ -169,7 +169,7 @@ static void si_launch_grid(
 				(struct pipe_resource*)kernel_args_buffer);
 	kernel_args_va += kernel_args_offset;
 
-	si_pm4_add_bo(pm4, kernel_args_buffer, RADEON_USAGE_READ);
+	si_pm4_add_bo(pm4, kernel_args_buffer, RADEON_USAGE_READ, RADEON_PRIO_SHADER_DATA);
 
 	si_pm4_set_reg(pm4, R_00B900_COMPUTE_USER_DATA_0, kernel_args_va);
 	si_pm4_set_reg(pm4, R_00B900_COMPUTE_USER_DATA_0 + 4, S_008F04_BASE_ADDRESS_HI (kernel_args_va >> 32) | S_008F04_STRIDE(0));
@@ -192,7 +192,7 @@ static void si_launch_grid(
 		if (!buffer) {
 			continue;
 		}
-		si_pm4_add_bo(pm4, buffer, RADEON_USAGE_READWRITE);
+		si_pm4_add_bo(pm4, buffer, RADEON_USAGE_READWRITE, RADEON_PRIO_SHADER_RESOURCE_RW);
 	}
 
 	/* This register has been moved to R_00CD20_COMPUTE_MAX_WAVE_ID
@@ -209,7 +209,7 @@ static void si_launch_grid(
 	}
 
 	shader_va = r600_resource_va(ctx->screen, (void *)shader->bo);
-	si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ);
+	si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_DATA);
 	si_pm4_set_reg(pm4, R_00B830_COMPUTE_PGM_LO, (shader_va >> 8) & 0xffffffff);
 	si_pm4_set_reg(pm4, R_00B834_COMPUTE_PGM_HI, shader_va >> 40);
 
diff --git a/src/gallium/drivers/radeonsi/si_descriptors.c b/src/gallium/drivers/radeonsi/si_descriptors.c
index 6b0ff91c2bc..bf2206dc1bc 100644
--- a/src/gallium/drivers/radeonsi/si_descriptors.c
+++ b/src/gallium/drivers/radeonsi/si_descriptors.c
@@ -129,7 +129,8 @@ static void si_init_descriptors(struct si_context *sctx,
 				   PIPE_USAGE_DEFAULT,
 				   SI_NUM_CONTEXTS * desc->context_size);
 
-	r600_context_bo_reloc(&sctx->b, &sctx->b.rings.gfx, desc->buffer, RADEON_USAGE_READWRITE);
+	r600_context_bo_reloc(&sctx->b, &sctx->b.rings.gfx, desc->buffer,
+			      RADEON_USAGE_READWRITE, RADEON_PRIO_SHADER_DATA);
 	va = r600_resource_va(sctx->b.b.screen, &desc->buffer->b.b);
 
 	/* We don't check for CS space here, because this should be called
@@ -301,6 +302,17 @@ static void si_release_sampler_views(struct si_sampler_views *views)
 	si_release_descriptors(&views->desc);
 }
 
+static enum radeon_bo_priority si_get_resource_ro_priority(struct r600_resource *res)
+{
+	if (res->b.b.target == PIPE_BUFFER)
+		return RADEON_PRIO_SHADER_BUFFER_RO;
+
+	if (res->b.b.nr_samples > 1)
+		return RADEON_PRIO_SHADER_TEXTURE_MSAA;
+
+	return RADEON_PRIO_SHADER_TEXTURE_RO;
+}
+
 static void si_sampler_views_begin_new_cs(struct si_context *sctx,
 					  struct si_sampler_views *views)
 {
@@ -312,10 +324,13 @@ static void si_sampler_views_begin_new_cs(struct si_context *sctx,
 		struct si_pipe_sampler_view *rview =
 			(struct si_pipe_sampler_view*)views->views[i];
 
-		r600_context_bo_reloc(&sctx->b, &sctx->b.rings.gfx, rview->resource, RADEON_USAGE_READ);
+		r600_context_bo_reloc(&sctx->b, &sctx->b.rings.gfx,
+				      rview->resource, RADEON_USAGE_READ,
+				      si_get_resource_ro_priority(rview->resource));
 	}
 
-	r600_context_bo_reloc(&sctx->b, &sctx->b.rings.gfx, views->desc.buffer, RADEON_USAGE_READWRITE);
+	r600_context_bo_reloc(&sctx->b, &sctx->b.rings.gfx, views->desc.buffer,
+			      RADEON_USAGE_READWRITE, RADEON_PRIO_SHADER_DATA);
 
 	si_emit_shader_pointer(sctx, &views->desc);
 }
@@ -333,7 +348,9 @@ void si_set_sampler_view(struct si_context *sctx, unsigned shader,
 		struct si_pipe_sampler_view *rview =
 			(struct si_pipe_sampler_view*)view;
 
-		r600_context_bo_reloc(&sctx->b, &sctx->b.rings.gfx, rview->resource, RADEON_USAGE_READ);
+		r600_context_bo_reloc(&sctx->b, &sctx->b.rings.gfx,
+				      rview->resource, RADEON_USAGE_READ,
+				      si_get_resource_ro_priority(rview->resource));
 
 		pipe_sampler_view_reference(&views->views[slot], view);
 		views->desc_data[slot] = view_desc;
@@ -361,12 +378,14 @@ static void si_init_buffer_resources(struct si_context *sctx,
 				     struct si_buffer_resources *buffers,
 				     unsigned num_buffers, unsigned shader,
 				     unsigned shader_userdata_index,
-				     enum radeon_bo_usage shader_usage)
+				     enum radeon_bo_usage shader_usage,
+				     enum radeon_bo_priority priority)
 {
 	int i;
 
 	buffers->num_buffers = num_buffers;
 	buffers->shader_usage = shader_usage;
+	buffers->priority = priority;
 	buffers->buffers = CALLOC(num_buffers, sizeof(struct pipe_resource*));
 	buffers->desc_storage = CALLOC(num_buffers, sizeof(uint32_t) * 4);
 
@@ -408,11 +427,12 @@ static void si_buffer_resources_begin_new_cs(struct si_context *sctx,
 
 		r600_context_bo_reloc(&sctx->b, &sctx->b.rings.gfx,
 				      (struct r600_resource*)buffers->buffers[i],
-				      buffers->shader_usage);
+				      buffers->shader_usage, buffers->priority);
 	}
 
 	r600_context_bo_reloc(&sctx->b, &sctx->b.rings.gfx,
-			      buffers->desc.buffer, RADEON_USAGE_READWRITE);
+			      buffers->desc.buffer, RADEON_USAGE_READWRITE,
+			      RADEON_PRIO_SHADER_DATA);
 
 	si_emit_shader_pointer(sctx, &buffers->desc);
 }
@@ -495,7 +515,8 @@ static void si_set_constant_buffer(struct pipe_context *ctx, uint shader, uint s
 
 		buffers->buffers[slot] = buffer;
 		r600_context_bo_reloc(&sctx->b, &sctx->b.rings.gfx,
-				      (struct r600_resource*)buffer, buffers->shader_usage);
+				      (struct r600_resource*)buffer,
+				      buffers->shader_usage, buffers->priority);
 		buffers->desc.enabled_mask |= 1 << slot;
 	} else {
 		/* Clear the descriptor. */
@@ -588,7 +609,7 @@ void si_set_ring_buffer(struct pipe_context *ctx, uint shader, uint slot,
 		pipe_resource_reference(&buffers->buffers[slot], input->buffer);
 		r600_context_bo_reloc(&sctx->b, &sctx->b.rings.gfx,
 				      (struct r600_resource*)input->buffer,
-				      buffers->shader_usage);
+				      buffers->shader_usage, buffers->priority);
 		buffers->desc.enabled_mask |= 1 << slot;
 	} else {
 		/* Clear the descriptor. */
@@ -643,7 +664,7 @@ static void si_set_streamout_targets(struct pipe_context *ctx,
 						buffer);
 			r600_context_bo_reloc(&sctx->b, &sctx->b.rings.gfx,
 					      (struct r600_resource*)buffer,
-					      buffers->shader_usage);
+					      buffers->shader_usage, buffers->priority);
 			buffers->desc.enabled_mask |= 1 << bufidx;
 		} else {
 			/* Clear the descriptor and unset the resource. */
@@ -731,7 +752,8 @@ static void si_invalidate_buffer(struct pipe_context *ctx, struct pipe_resource
 							    old_va, buf);
 
 				r600_context_bo_reloc(&sctx->b, &sctx->b.rings.gfx,
-						      rbuffer, buffers->shader_usage);
+						      rbuffer, buffers->shader_usage,
+						      buffers->priority);
 
 				buffers->desc.dirty_mask |= 1 << i;
 				found = true;
@@ -765,7 +787,8 @@ static void si_invalidate_buffer(struct pipe_context *ctx, struct pipe_resource
 							    old_va, buf);
 
 				r600_context_bo_reloc(&sctx->b, &sctx->b.rings.gfx,
-						      rbuffer, buffers->shader_usage);
+						      rbuffer, buffers->shader_usage,
+						      buffers->priority);
 
 				buffers->desc.dirty_mask |= 1 << i;
 				found = true;
@@ -790,7 +813,8 @@ static void si_invalidate_buffer(struct pipe_context *ctx, struct pipe_resource
 							    old_va, buf);
 
 				r600_context_bo_reloc(&sctx->b, &sctx->b.rings.gfx,
-						      rbuffer, RADEON_USAGE_READ);
+						      rbuffer, RADEON_USAGE_READ,
+						      RADEON_PRIO_SHADER_BUFFER_RO);
 
 				views->desc.dirty_mask |= 1 << i;
 				found = true;
@@ -853,7 +877,8 @@ static void si_clear_buffer(struct pipe_context *ctx, struct pipe_resource *dst,
 
 		/* This must be done after need_cs_space. */
 		r600_context_bo_reloc(&sctx->b, &sctx->b.rings.gfx,
-				      (struct r600_resource*)dst, RADEON_USAGE_WRITE);
+				      (struct r600_resource*)dst, RADEON_USAGE_WRITE,
+				      RADEON_PRIO_MIN);
 
 		/* Flush the caches for the first copy only.
 		 * Also wait for the previous CP DMA operations. */
@@ -927,8 +952,10 @@ void si_copy_buffer(struct si_context *sctx,
 		}
 
 		/* This must be done after r600_need_cs_space. */
-		r600_context_bo_reloc(&sctx->b, &sctx->b.rings.gfx, (struct r600_resource*)src, RADEON_USAGE_READ);
-		r600_context_bo_reloc(&sctx->b, &sctx->b.rings.gfx, (struct r600_resource*)dst, RADEON_USAGE_WRITE);
+		r600_context_bo_reloc(&sctx->b, &sctx->b.rings.gfx, (struct r600_resource*)src,
+				      RADEON_USAGE_READ, RADEON_PRIO_MIN);
+		r600_context_bo_reloc(&sctx->b, &sctx->b.rings.gfx, (struct r600_resource*)dst,
+				      RADEON_USAGE_WRITE, RADEON_PRIO_MIN);
 
 		si_emit_cp_dma_copy_buffer(sctx, dst_offset, src_offset, byte_count, sync_flags);
 
@@ -954,12 +981,12 @@ void si_init_all_descriptors(struct si_context *sctx)
 	for (i = 0; i < SI_NUM_SHADERS; i++) {
 		si_init_buffer_resources(sctx, &sctx->const_buffers[i],
 					 NUM_CONST_BUFFERS, i, SI_SGPR_CONST,
-					 RADEON_USAGE_READ);
+					 RADEON_USAGE_READ, RADEON_PRIO_SHADER_BUFFER_RO);
 		si_init_buffer_resources(sctx, &sctx->rw_buffers[i],
 					 i == PIPE_SHADER_VERTEX ?
 					 SI_RW_SO + 4 : SI_RW_SO,
 					 i, SI_SGPR_RW_BUFFERS,
-					 RADEON_USAGE_READWRITE);
+					 RADEON_USAGE_READWRITE, RADEON_PRIO_SHADER_RESOURCE_RW);
 
 		si_init_sampler_views(sctx, &sctx->samplers[i].views, i);
 
diff --git a/src/gallium/drivers/radeonsi/si_pm4.c b/src/gallium/drivers/radeonsi/si_pm4.c
index 0a5673ba917..082da85e03d 100644
--- a/src/gallium/drivers/radeonsi/si_pm4.c
+++ b/src/gallium/drivers/radeonsi/si_pm4.c
@@ -92,13 +92,15 @@ void si_pm4_set_reg(struct si_pm4_state *state, unsigned reg, uint32_t val)
 
 void si_pm4_add_bo(struct si_pm4_state *state,
                    struct r600_resource *bo,
-                   enum radeon_bo_usage usage)
+                   enum radeon_bo_usage usage,
+		   enum radeon_bo_priority priority)
 {
 	unsigned idx = state->nbo++;
 	assert(idx < SI_PM4_MAX_BO);
 
 	r600_resource_reference(&state->bo[idx], bo);
 	state->bo_usage[idx] = usage;
+	state->bo_priority[idx] = priority;
 }
 
 void si_pm4_sh_data_begin(struct si_pm4_state *state)
@@ -215,7 +217,7 @@ void si_pm4_emit(struct si_context *sctx, struct si_pm4_state *state)
 	struct radeon_winsys_cs *cs = sctx->b.rings.gfx.cs;
 	for (int i = 0; i < state->nbo; ++i) {
 		r600_context_bo_reloc(&sctx->b, &sctx->b.rings.gfx, state->bo[i],
-				      state->bo_usage[i]);
+				      state->bo_usage[i], state->bo_priority[i]);
 	}
 
 	memcpy(&cs->buf[cs->cdw], state->pm4, state->ndw * 4);
diff --git a/src/gallium/drivers/radeonsi/si_pm4.h b/src/gallium/drivers/radeonsi/si_pm4.h
index e1d0cac3b73..a71958601aa 100644
--- a/src/gallium/drivers/radeonsi/si_pm4.h
+++ b/src/gallium/drivers/radeonsi/si_pm4.h
@@ -57,6 +57,7 @@ struct si_pm4_state
 	unsigned		nbo;
 	struct r600_resource	*bo[SI_PM4_MAX_BO];
 	enum radeon_bo_usage	bo_usage[SI_PM4_MAX_BO];
+	enum radeon_bo_priority	bo_priority[SI_PM4_MAX_BO];
 
 	/* relocs for shader data */
 	unsigned	nrelocs;
@@ -72,7 +73,8 @@ void si_pm4_cmd_end(struct si_pm4_state *state, bool predicate);
 void si_pm4_set_reg(struct si_pm4_state *state, unsigned reg, uint32_t val);
 void si_pm4_add_bo(struct si_pm4_state *state,
 		   struct r600_resource *bo,
-		   enum radeon_bo_usage usage);
+		   enum radeon_bo_usage usage,
+		   enum radeon_bo_priority priority);
 
 void si_pm4_sh_data_begin(struct si_pm4_state *state);
 void si_pm4_sh_data_add(struct si_pm4_state *state, uint32_t dw);
diff --git a/src/gallium/drivers/radeonsi/si_state.c b/src/gallium/drivers/radeonsi/si_state.c
index 7d4f3c7409d..7734e35876e 100644
--- a/src/gallium/drivers/radeonsi/si_state.c
+++ b/src/gallium/drivers/radeonsi/si_state.c
@@ -2064,7 +2064,9 @@ static void si_set_framebuffer_state(struct pipe_context *ctx,
 			sctx->fb_compressed_cb_mask |= 1 << i;
 		}
 
-		si_pm4_add_bo(pm4, &rtex->resource, RADEON_USAGE_READWRITE);
+		si_pm4_add_bo(pm4, &rtex->resource, RADEON_USAGE_READWRITE,
+			      rtex->surface.nsamples > 1 ? RADEON_PRIO_COLOR_BUFFER_MSAA :
+							   RADEON_PRIO_COLOR_BUFFER);
 		si_pm4_set_reg(pm4, R_028C60_CB_COLOR0_BASE + i * 0x3C, surf->cb_color_base);
 		si_pm4_set_reg(pm4, R_028C64_CB_COLOR0_PITCH + i * 0x3C, surf->cb_color_pitch);
 		si_pm4_set_reg(pm4, R_028C68_CB_COLOR0_SLICE + i * 0x3C, surf->cb_color_slice);
@@ -2101,7 +2103,8 @@ static void si_set_framebuffer_state(struct pipe_context *ctx,
 		}
 
 		if (surf->db_htile_data_base) {
-			si_pm4_add_bo(pm4, rtex->htile_buffer, RADEON_USAGE_READWRITE);
+			si_pm4_add_bo(pm4, rtex->htile_buffer, RADEON_USAGE_READWRITE,
+				      RADEON_PRIO_DEPTH_META);
 		}
 		si_pm4_set_reg(pm4, R_028008_DB_DEPTH_VIEW, surf->db_depth_view);
 		si_pm4_set_reg(pm4, R_028014_DB_HTILE_DATA_BASE, surf->db_htile_data_base);
@@ -2109,7 +2112,9 @@ static void si_set_framebuffer_state(struct pipe_context *ctx,
 		si_pm4_set_reg(pm4, R_02803C_DB_DEPTH_INFO, surf->db_depth_info);
 		si_pm4_set_reg(pm4, R_028040_DB_Z_INFO, surf->db_z_info);
 		si_pm4_set_reg(pm4, R_028044_DB_STENCIL_INFO, surf->db_stencil_info);
-		si_pm4_add_bo(pm4, &rtex->resource, RADEON_USAGE_READWRITE);
+		si_pm4_add_bo(pm4, &rtex->resource, RADEON_USAGE_READWRITE,
+			      rtex->surface.nsamples > 1 ? RADEON_PRIO_DEPTH_BUFFER_MSAA :
+							   RADEON_PRIO_DEPTH_BUFFER);
 		si_pm4_set_reg(pm4, R_028048_DB_Z_READ_BASE, surf->db_depth_base);
 		si_pm4_set_reg(pm4, R_02804C_DB_STENCIL_READ_BASE, surf->db_stencil_base);
 		si_pm4_set_reg(pm4, R_028050_DB_Z_WRITE_BASE, surf->db_depth_base);
@@ -2863,7 +2868,8 @@ static void si_set_sampler_states(struct si_context *sctx,
 		if (sctx->b.chip_class >= CIK)
 			si_pm4_set_reg(pm4, R_028084_TA_BC_BASE_ADDR_HI, va_offset >> 40);
 		sctx->b.ws->buffer_unmap(sctx->border_color_table->cs_buf);
-		si_pm4_add_bo(pm4, sctx->border_color_table, RADEON_USAGE_READ);
+		si_pm4_add_bo(pm4, sctx->border_color_table, RADEON_USAGE_READ,
+			      RADEON_PRIO_SHADER_DATA);
 	}
 
 	memcpy(samplers->samplers, states, sizeof(void*) * count);
diff --git a/src/gallium/drivers/radeonsi/si_state.h b/src/gallium/drivers/radeonsi/si_state.h
index fbc0d231226..0bd4e0551d2 100644
--- a/src/gallium/drivers/radeonsi/si_state.h
+++ b/src/gallium/drivers/radeonsi/si_state.h
@@ -162,6 +162,7 @@ struct si_buffer_resources {
 	struct si_descriptors		desc;
 	unsigned			num_buffers;
 	enum radeon_bo_usage		shader_usage; /* READ, WRITE, or READWRITE */
+	enum radeon_bo_priority		priority;
 	struct pipe_resource		**buffers; /* this has num_buffers elements */
 	uint32_t			*desc_storage; /* this has num_buffers*4 elements */
 	uint32_t			**desc_data; /* an array of pointers pointing to desc_storage */
diff --git a/src/gallium/drivers/radeonsi/si_state_draw.c b/src/gallium/drivers/radeonsi/si_state_draw.c
index 480e3f8a520..7321d1dd385 100644
--- a/src/gallium/drivers/radeonsi/si_state_draw.c
+++ b/src/gallium/drivers/radeonsi/si_state_draw.c
@@ -54,7 +54,7 @@ static void si_pipe_shader_es(struct pipe_context *ctx, struct si_pipe_shader *s
 		return;
 
 	va = r600_resource_va(ctx->screen, (void *)shader->bo);
-	si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ);
+	si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_DATA);
 
 	vgpr_comp_cnt = shader->shader.uses_instanceid ? 3 : 0;
 
@@ -129,7 +129,7 @@ static void si_pipe_shader_gs(struct pipe_context *ctx, struct si_pipe_shader *s
 	si_pm4_set_reg(pm4, R_028B5C_VGT_GS_VERT_ITEMSIZE, gs_vert_itemsize);
 
 	va = r600_resource_va(ctx->screen, (void *)shader->bo);
-	si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ);
+	si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_DATA);
 	si_pm4_set_reg(pm4, R_00B220_SPI_SHADER_PGM_LO_GS, va >> 8);
 	si_pm4_set_reg(pm4, R_00B224_SPI_SHADER_PGM_HI_GS, va >> 40);
 
@@ -166,7 +166,7 @@ static void si_pipe_shader_vs(struct pipe_context *ctx, struct si_pipe_shader *s
 		return;
 
 	va = r600_resource_va(ctx->screen, (void *)shader->bo);
-	si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ);
+	si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_DATA);
 
 	vgpr_comp_cnt = shader->shader.uses_instanceid ? 3 : 0;
 
@@ -315,7 +315,7 @@ static void si_pipe_shader_ps(struct pipe_context *ctx, struct si_pipe_shader *s
 	si_pm4_set_reg(pm4, R_02823C_CB_SHADER_MASK, shader->cb_shader_mask);
 
 	va = r600_resource_va(ctx->screen, (void *)shader->bo);
-	si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ);
+	si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_DATA);
 	si_pm4_set_reg(pm4, R_00B020_SPI_SHADER_PGM_LO_PS, va >> 8);
 	si_pm4_set_reg(pm4, R_00B024_SPI_SHADER_PGM_HI_PS, va >> 40);
 
@@ -728,7 +728,8 @@ static void si_vertex_buffer_update(struct si_context *sctx)
 		si_pm4_sh_data_add(pm4, sctx->vertex_elements->rsrc_word3[i]);
 
 		if (!bound[ve->vertex_buffer_index]) {
-			si_pm4_add_bo(pm4, rbuffer, RADEON_USAGE_READ);
+			si_pm4_add_bo(pm4, rbuffer, RADEON_USAGE_READ,
+				      RADEON_PRIO_SHADER_BUFFER_RO);
 			bound[ve->vertex_buffer_index] = true;
 		}
 	}
@@ -784,7 +785,8 @@ static void si_state_draw(struct si_context *sctx,
 		si_pm4_cmd_add(pm4, va >> 32UL); /* src address hi */
 		si_pm4_cmd_add(pm4, R_028B2C_VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE >> 2);
 		si_pm4_cmd_add(pm4, 0); /* unused */
-		si_pm4_add_bo(pm4, t->buf_filled_size, RADEON_USAGE_READ);
+		si_pm4_add_bo(pm4, t->buf_filled_size, RADEON_USAGE_READ,
+			      RADEON_PRIO_MIN);
 		si_pm4_cmd_end(pm4, true);
 	}
 
@@ -810,7 +812,8 @@ static void si_state_draw(struct si_context *sctx,
 		va = r600_resource_va(&sctx->screen->b.b, ib->buffer);
 		va += ib->offset;
 
-		si_pm4_add_bo(pm4, (struct r600_resource *)ib->buffer, RADEON_USAGE_READ);
+		si_pm4_add_bo(pm4, (struct r600_resource *)ib->buffer, RADEON_USAGE_READ,
+			      RADEON_PRIO_MIN);
 		si_cmd_draw_index_2(pm4, max_size, va, info->count,
 				    V_0287F0_DI_SRC_SEL_DMA,
 				    sctx->b.predicate_drawing);