diff options
| author | Marek Olšák <[email protected]> | 2016-12-08 16:54:24 +0100 |
|---|---|---|
| committer | Marek Olšák <[email protected]> | 2017-03-30 14:44:33 +0200 |
| commit | b0547182185fd840322a0acdea8fe06a7318b96b (patch) | |
| tree | 83f72b2ff4109bdd80d36d23edb14e66661ba086 /src/gallium/drivers/radeonsi | |
| parent | de7967a27a0830c6c9537e138d02a2224e426909 (diff) | |
radeonsi/gfx9: don't set PA_SC_RASTER_CONFIG*
The registers don't exist on GFX9.
Reviewed-by: Nicolai Hähnle <[email protected]>
Diffstat (limited to 'src/gallium/drivers/radeonsi')
| -rw-r--r-- | src/gallium/drivers/radeonsi/si_state.c | 34 |
1 files changed, 19 insertions, 15 deletions
diff --git a/src/gallium/drivers/radeonsi/si_state.c b/src/gallium/drivers/radeonsi/si_state.c index acfa809376c..772b8ce3417 100644 --- a/src/gallium/drivers/radeonsi/si_state.c +++ b/src/gallium/drivers/radeonsi/si_state.c @@ -4081,24 +4081,28 @@ static void si_init_config(struct si_context *sctx) raster_config_1 = 0x00000000; break; default: - fprintf(stderr, - "radeonsi: Unknown GPU, using 0 for raster_config\n"); - raster_config = 0x00000000; - raster_config_1 = 0x00000000; + if (sctx->b.chip_class <= VI) { + fprintf(stderr, + "radeonsi: Unknown GPU, using 0 for raster_config\n"); + raster_config = 0x00000000; + raster_config_1 = 0x00000000; + } break; } - /* Always use the default config when all backends are enabled - * (or when we failed to determine the enabled backends). - */ - if (!rb_mask || util_bitcount(rb_mask) >= num_rb) { - si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, - raster_config); - if (sctx->b.chip_class >= CIK) - si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1, - raster_config_1); - } else { - si_write_harvested_raster_configs(sctx, pm4, raster_config, raster_config_1); + if (sctx->b.chip_class <= VI) { + if (!rb_mask || util_bitcount(rb_mask) >= num_rb) { + /* Always use the default config when all backends are enabled + * (or when we failed to determine the enabled backends). + */ + si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, + raster_config); + if (sctx->b.chip_class >= CIK) + si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1, + raster_config_1); + } else { + si_write_harvested_raster_configs(sctx, pm4, raster_config, raster_config_1); + } } si_pm4_set_reg(pm4, R_028204_PA_SC_WINDOW_SCISSOR_TL, S_028204_WINDOW_OFFSET_DISABLE(1)); |