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authorMarek Olšák <[email protected]>2017-02-15 18:32:34 +0100
committerMarek Olšák <[email protected]>2017-02-18 01:22:08 +0100
commit791e8ce04a7e9970f437858bdff0a1f8b47626ba (patch)
treea3a487420cede820b38ad5f4e04c1c4835963448 /src/gallium/drivers/radeonsi
parentd6c8c26851c5fe03a6a21b2280be216aae6bbe33 (diff)
radeonsi: use a clever alignment for index buffer uploads
Reviewed-by: Nicolai Hähnle <[email protected]>
Diffstat (limited to 'src/gallium/drivers/radeonsi')
-rw-r--r--src/gallium/drivers/radeonsi/si_state_draw.c11
1 files changed, 7 insertions, 4 deletions
diff --git a/src/gallium/drivers/radeonsi/si_state_draw.c b/src/gallium/drivers/radeonsi/si_state_draw.c
index e341f33fb1a..34a44cc31fd 100644
--- a/src/gallium/drivers/radeonsi/si_state_draw.c
+++ b/src/gallium/drivers/radeonsi/si_state_draw.c
@@ -1048,14 +1048,16 @@ void si_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info)
/* 8-bit indices are supported on VI. */
if (sctx->b.chip_class <= CIK && ib.index_size == 1) {
struct pipe_resource *out_buffer = NULL;
- unsigned out_offset, start, count, start_offset;
+ unsigned out_offset, start, count, start_offset, size;
void *ptr;
si_get_draw_start_count(sctx, info, &start, &count);
start_offset = start * ib.index_size;
+ size = count * 2;
u_upload_alloc(ctx->stream_uploader, start_offset,
- count * 2, 256,
+ size,
+ si_optimal_tcc_alignment(sctx, size),
&out_offset, &out_buffer, &ptr);
if (!out_buffer) {
pipe_resource_reference(&ib.buffer, NULL);
@@ -1079,8 +1081,9 @@ void si_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info)
start_offset = start * ib.index_size;
u_upload_data(ctx->stream_uploader, start_offset,
- count * ib.index_size,
- 256, (char*)ib.user_buffer + start_offset,
+ count * ib.index_size,
+ sctx->screen->b.info.tcc_cache_line_size,
+ (char*)ib.user_buffer + start_offset,
&ib.offset, &ib.buffer);
if (!ib.buffer)
return;