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authorMarek Olšák <[email protected]>2014-09-20 11:54:46 +0200
committerMarek Olšák <[email protected]>2014-09-24 14:48:02 +0200
commitdd53d53dc664946a445bcb9e26b1819f4b92a32c (patch)
treef1f2d110c6ad47562a07fef3c788a712a841750f /src/gallium/drivers/radeonsi
parent604b58b554f00ab9eb06eff47bfd4f859424c0ae (diff)
radeonsi/compute: do CS partial flush with si_emit_cache_flush
Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Tom Stellard <[email protected]>
Diffstat (limited to 'src/gallium/drivers/radeonsi')
-rw-r--r--src/gallium/drivers/radeonsi/si_compute.c7
-rw-r--r--src/gallium/drivers/radeonsi/si_state_draw.c7
2 files changed, 8 insertions, 6 deletions
diff --git a/src/gallium/drivers/radeonsi/si_compute.c b/src/gallium/drivers/radeonsi/si_compute.c
index e24c6e22bb4..be644181796 100644
--- a/src/gallium/drivers/radeonsi/si_compute.c
+++ b/src/gallium/drivers/radeonsi/si_compute.c
@@ -361,10 +361,6 @@ static void si_launch_grid(
si_pm4_cmd_add(pm4, 1); /* DISPATCH_INITIATOR */
si_pm4_cmd_end(pm4, false);
- si_pm4_cmd_begin(pm4, PKT3_EVENT_WRITE);
- si_pm4_cmd_add(pm4, EVENT_TYPE(V_028A90_CS_PARTIAL_FLUSH | EVENT_INDEX(0x4)));
- si_pm4_cmd_end(pm4, false);
-
si_pm4_emit(sctx, pm4);
#if 0
@@ -376,7 +372,8 @@ static void si_launch_grid(
si_pm4_free_state(sctx, pm4, ~0);
- sctx->b.flags |= R600_CONTEXT_INV_TEX_CACHE |
+ sctx->b.flags |= R600_CONTEXT_CS_PARTIAL_FLUSH |
+ R600_CONTEXT_INV_TEX_CACHE |
R600_CONTEXT_INV_SHADER_CACHE |
R600_CONTEXT_INV_CONST_CACHE |
R600_CONTEXT_FLAG_COMPUTE;
diff --git a/src/gallium/drivers/radeonsi/si_state_draw.c b/src/gallium/drivers/radeonsi/si_state_draw.c
index a4b70177ea9..0888841f4a8 100644
--- a/src/gallium/drivers/radeonsi/si_state_draw.c
+++ b/src/gallium/drivers/radeonsi/si_state_draw.c
@@ -863,6 +863,11 @@ void si_emit_cache_flush(struct r600_common_context *sctx, struct r600_atom *ato
radeon_emit(cs, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4));
}
+ if (sctx->flags & R600_CONTEXT_CS_PARTIAL_FLUSH) {
+ radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0) | compute);
+ radeon_emit(cs, EVENT_TYPE(V_028A90_CS_PARTIAL_FLUSH | EVENT_INDEX(4)));
+ }
+
if (sctx->flags & R600_CONTEXT_VGT_FLUSH) {
radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0) | compute);
radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
@@ -875,7 +880,7 @@ void si_emit_cache_flush(struct r600_common_context *sctx, struct r600_atom *ato
sctx->flags = 0;
}
-const struct r600_atom si_atom_cache_flush = { si_emit_cache_flush, 19 }; /* number of CS dwords */
+const struct r600_atom si_atom_cache_flush = { si_emit_cache_flush, 21 }; /* number of CS dwords */
static void si_get_draw_start_count(struct si_context *sctx,
const struct pipe_draw_info *info,