diff options
| author | Nicolai Hähnle <[email protected]> | 2018-07-23 09:47:19 +0200 |
|---|---|---|
| committer | Marek Olšák <[email protected]> | 2019-07-03 15:51:13 -0400 |
| commit | d028440f578fb2ab96e64846c8f378bd6b247886 (patch) | |
| tree | 89865332704024b48871a54e8935bc4f2435b4be /src/gallium/drivers/radeonsi | |
| parent | 1666ee183e2dd0ae78cbec236315ad6328692589 (diff) | |
radeonsi/gfx10: mask DCC tile swizzle by alignment
DCC alignment can be less than the alignment of the main surface. In that
case, the DCC tile swizzle needs to be masked accordingly. Should have no
impact on pre-gfx10.
Acked-by: Bas Nieuwenhuizen <[email protected]>
Diffstat (limited to 'src/gallium/drivers/radeonsi')
| -rw-r--r-- | src/gallium/drivers/radeonsi/si_descriptors.c | 4 | ||||
| -rw-r--r-- | src/gallium/drivers/radeonsi/si_state.c | 5 |
2 files changed, 7 insertions, 2 deletions
diff --git a/src/gallium/drivers/radeonsi/si_descriptors.c b/src/gallium/drivers/radeonsi/si_descriptors.c index 262f7e88c93..5a8c4acc53a 100644 --- a/src/gallium/drivers/radeonsi/si_descriptors.c +++ b/src/gallium/drivers/radeonsi/si_descriptors.c @@ -351,7 +351,9 @@ void si_set_mutable_tex_desc_fields(struct si_screen *sscreen, assert(base_level_info->mode == RADEON_SURF_MODE_2D); } - meta_va |= (uint32_t)tex->surface.tile_swizzle << 8; + unsigned dcc_tile_swizzle = tex->surface.tile_swizzle << 8; + dcc_tile_swizzle &= tex->surface.dcc_alignment - 1; + meta_va |= dcc_tile_swizzle; } else if (vi_tc_compat_htile_enabled(tex, first_level)) { meta_va = tex->buffer.gpu_address + tex->htile_offset; } diff --git a/src/gallium/drivers/radeonsi/si_state.c b/src/gallium/drivers/radeonsi/si_state.c index 0044353fd66..685ce697b3a 100644 --- a/src/gallium/drivers/radeonsi/si_state.c +++ b/src/gallium/drivers/radeonsi/si_state.c @@ -3194,7 +3194,10 @@ static void si_emit_framebuffer_state(struct si_context *sctx) cb_dcc_base = ((!tex->dcc_separate_buffer ? tex->buffer.gpu_address : 0) + tex->dcc_offset) >> 8; - cb_dcc_base |= tex->surface.tile_swizzle; + + unsigned dcc_tile_swizzle = tex->surface.tile_swizzle; + dcc_tile_swizzle &= (tex->surface.dcc_alignment - 1) >> 8; + cb_dcc_base |= dcc_tile_swizzle; } if (sctx->chip_class >= GFX10) { |