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authorMarek Olšák <[email protected]>2016-11-06 19:27:09 +0100
committerMarek Olšák <[email protected]>2017-03-30 14:44:33 +0200
commit86f13c7363a6acedc01144c7fc70f8bcac0c43d7 (patch)
tree10c640f9b8099a6a758803e9b5d6e85415640ecc /src/gallium/drivers/radeonsi
parentad93d72c340fc41263d1fa6790ab56c4e10e6244 (diff)
radeonsi/gfx9: emit FLUSH_DFSM where required
Reviewed-by: Nicolai Hähnle <[email protected]>
Diffstat (limited to 'src/gallium/drivers/radeonsi')
-rw-r--r--src/gallium/drivers/radeonsi/si_pipe.h1
-rw-r--r--src/gallium/drivers/radeonsi/si_state.c17
2 files changed, 18 insertions, 0 deletions
diff --git a/src/gallium/drivers/radeonsi/si_pipe.h b/src/gallium/drivers/radeonsi/si_pipe.h
index 174baaa01d3..e1df3b65261 100644
--- a/src/gallium/drivers/radeonsi/si_pipe.h
+++ b/src/gallium/drivers/radeonsi/si_pipe.h
@@ -259,6 +259,7 @@ struct si_context {
struct r600_atom msaa_config;
struct si_sample_mask sample_mask;
struct r600_atom cb_render_state;
+ unsigned last_cb_target_mask;
struct si_blend_color blend_color;
struct r600_atom clip_regs;
struct si_clip_state clip_state;
diff --git a/src/gallium/drivers/radeonsi/si_state.c b/src/gallium/drivers/radeonsi/si_state.c
index 1b7aaa9a690..f6c6f1f2dc5 100644
--- a/src/gallium/drivers/radeonsi/si_state.c
+++ b/src/gallium/drivers/radeonsi/si_state.c
@@ -117,6 +117,17 @@ static void si_emit_cb_render_state(struct si_context *sctx, struct r600_atom *a
radeon_set_context_reg(cs, R_028238_CB_TARGET_MASK, cb_target_mask);
+ /* GFX9: Flush DFSM when CB_TARGET_MASK changes.
+ * I think we don't have to do anything between IBs.
+ */
+ if (sctx->b.chip_class >= GFX9 &&
+ sctx->last_cb_target_mask != cb_target_mask) {
+ sctx->last_cb_target_mask = cb_target_mask;
+
+ radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
+ radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
+ }
+
/* RB+ register settings. */
if (sctx->screen->b.rbplus_allowed) {
unsigned spi_shader_col_format =
@@ -2877,6 +2888,12 @@ static void si_emit_msaa_config(struct si_context *sctx, struct r600_atom *atom)
sctx->ps_iter_samples,
sctx->smoothing_enabled ? SI_NUM_SMOOTH_AA_SAMPLES : 0,
sc_mode_cntl_1);
+
+ /* GFX9: Flush DFSM when the AA mode changes. */
+ if (sctx->b.chip_class >= GFX9) {
+ radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
+ radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
+ }
}
static void si_set_min_samples(struct pipe_context *ctx, unsigned min_samples)