radeonsi: use storage_samples instead of color_samples in most places

and use pipe_resource::nr_storage_samples instead of
r600_texture::num_color_samples.

Tested-by: Dieter Nützel <[email protected]>

4 files changed, 24 insertions, 38 deletions

diff --git a/src/gallium/drivers/radeonsi/si_clear.c b/src/gallium/drivers/radeonsi/si_clear.c
index e614ab52423..4e07de81bac 100644
--- a/src/gallium/drivers/radeonsi/si_clear.c
+++ b/src/gallium/drivers/radeonsi/si_clear.c
@@ -237,7 +237,7 @@ void vi_dcc_clear_level(struct si_context *sctx,
 		assert(tex->buffer.b.b.last_level == 0);
 		/* 4x and 8x MSAA needs a sophisticated compute shader for
 		 * the clear. See AMDVLK. */
-		assert(tex->num_color_samples <= 2);
+		assert(tex->buffer.b.b.nr_storage_samples <= 2);
 		clear_size = tex->surface.dcc_size;
 	} else {
 		unsigned num_layers = util_num_layers(&tex->buffer.b.b, level);
@@ -248,7 +248,7 @@ void vi_dcc_clear_level(struct si_context *sctx,
 		 * dcc_fast_clear_size bytes for each layer. A compute shader
 		 * would be more efficient than separate per-layer clear operations.
 		 */
-		assert(tex->num_color_samples <= 2 || num_layers == 1);
+		assert(tex->buffer.b.b.nr_storage_samples <= 2 || num_layers == 1);
 
 		dcc_offset += tex->surface.u.legacy.level[level].dcc_offset;
 		clear_size = tex->surface.u.legacy.level[level].dcc_fast_clear_size *
diff --git a/src/gallium/drivers/radeonsi/si_pipe.h b/src/gallium/drivers/radeonsi/si_pipe.h
index 4a3e8bba18e..9ab79bcaa2e 100644
--- a/src/gallium/drivers/radeonsi/si_pipe.h
+++ b/src/gallium/drivers/radeonsi/si_pipe.h
@@ -248,7 +248,6 @@ struct si_texture {
 	unsigned			color_clear_value[2];
 	unsigned			last_msaa_resolve_target_micro_mode;
 	unsigned			num_level0_transfers;
-	unsigned			num_color_samples;
 
 	/* Depth buffer compression and fast clear. */
 	uint64_t			htile_offset;
diff --git a/src/gallium/drivers/radeonsi/si_state.c b/src/gallium/drivers/radeonsi/si_state.c
index fc5d63f02d3..a1b00cb979a 100644
--- a/src/gallium/drivers/radeonsi/si_state.c
+++ b/src/gallium/drivers/radeonsi/si_state.c
@@ -2431,7 +2431,7 @@ static void si_initialize_color_surface(struct si_context *sctx,
 
 	if (tex->buffer.b.b.nr_samples > 1) {
 		unsigned log_samples = util_logbase2(tex->buffer.b.b.nr_samples);
-		unsigned log_fragments = util_logbase2(tex->num_color_samples);
+		unsigned log_fragments = util_logbase2(tex->buffer.b.b.nr_storage_samples);
 
 		color_attrib |= S_028C74_NUM_SAMPLES(log_samples) |
 				S_028C74_NUM_FRAGMENTS(log_fragments);
@@ -2458,7 +2458,7 @@ static void si_initialize_color_surface(struct si_context *sctx,
 		if (!sctx->screen->info.has_dedicated_vram)
 			min_compressed_block_size = V_028C78_MIN_BLOCK_SIZE_64B;
 
-		if (tex->num_color_samples > 1) {
+		if (tex->buffer.b.b.nr_storage_samples > 1) {
 			if (tex->surface.bpe == 1)
 				max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_64B;
 			else if (tex->surface.bpe == 2)
@@ -2869,10 +2869,12 @@ static void si_set_framebuffer_state(struct pipe_context *ctx,
 		 * (e.g. destination of MSAA resolve)
 		 */
 		if (tex->buffer.b.b.nr_samples >= 2 &&
-		    tex->num_color_samples < tex->buffer.b.b.nr_samples) {
+		    tex->buffer.b.b.nr_storage_samples < tex->buffer.b.b.nr_samples) {
 			sctx->framebuffer.nr_color_samples =
 				MIN2(sctx->framebuffer.nr_color_samples,
-				     tex->num_color_samples);
+				     tex->buffer.b.b.nr_storage_samples);
+			sctx->framebuffer.nr_color_samples =
+				MAX2(1, sctx->framebuffer.nr_color_samples);
 		}
 
 		if (tex->surface.is_linear)
@@ -3633,7 +3635,8 @@ si_make_texture_descriptor(struct si_screen *screen,
 	desc = util_format_description(pipe_format);
 
 	num_samples = desc->colorspace == UTIL_FORMAT_COLORSPACE_ZS ?
-			MAX2(1, res->nr_samples) : tex->num_color_samples;
+			MAX2(1, res->nr_samples) :
+			MAX2(1, res->nr_storage_samples);
 
 	if (desc->colorspace == UTIL_FORMAT_COLORSPACE_ZS) {
 		const unsigned char swizzle_xxxx[4] = {0, 0, 0, 0};
@@ -3831,10 +3834,10 @@ si_make_texture_descriptor(struct si_screen *screen,
 
 		va = tex->buffer.gpu_address + tex->fmask_offset;
 
-#define FMASK(s,f) (((unsigned)(s) * 16) + (f))
+#define FMASK(s,f) (((unsigned)(MAX2(1, s)) * 16) + (MAX2(1, f)))
 		if (screen->info.chip_class >= GFX9) {
 			data_format = V_008F14_IMG_DATA_FORMAT_FMASK;
-			switch (FMASK(res->nr_samples, tex->num_color_samples)) {
+			switch (FMASK(res->nr_samples, res->nr_storage_samples)) {
 			case FMASK(2,1):
 				num_format = V_008F14_IMG_FMASK_8_2_1;
 				break;
@@ -3878,7 +3881,7 @@ si_make_texture_descriptor(struct si_screen *screen,
 				unreachable("invalid nr_samples");
 			}
 		} else {
-			switch (FMASK(res->nr_samples, tex->num_color_samples)) {
+			switch (FMASK(res->nr_samples, res->nr_storage_samples)) {
 			case FMASK(2,1):
 				data_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S2_F1;
 				break;
diff --git a/src/gallium/drivers/radeonsi/si_texture.c b/src/gallium/drivers/radeonsi/si_texture.c
index 46df4aecf09..e55fd815264 100644
--- a/src/gallium/drivers/radeonsi/si_texture.c
+++ b/src/gallium/drivers/radeonsi/si_texture.c
@@ -220,7 +220,6 @@ static unsigned si_texture_get_offset(struct si_screen *sscreen,
 static int si_init_surface(struct si_screen *sscreen,
 			   struct radeon_surf *surface,
 			   const struct pipe_resource *ptex,
-			   unsigned num_color_samples,
 			   enum radeon_surf_mode array_mode,
 			   unsigned pitch_in_bytes_override,
 			   unsigned offset,
@@ -280,13 +279,13 @@ static int si_init_surface(struct si_screen *sscreen,
 
 	/* VI: DCC clear for 4x and 8x MSAA array textures unimplemented. */
 	if (sscreen->info.chip_class == VI &&
-	    num_color_samples >= 4 &&
+	    ptex->nr_storage_samples >= 4 &&
 	    ptex->array_size > 1)
 		flags |= RADEON_SURF_DISABLE_DCC;
 
 	/* GFX9: DCC clear for 4x and 8x MSAA textures unimplemented. */
 	if (sscreen->info.chip_class >= GFX9 &&
-	    num_color_samples >= 4)
+	    ptex->nr_storage_samples >= 4)
 		flags |= RADEON_SURF_DISABLE_DCC;
 
 	if (ptex->bind & PIPE_BIND_SCANOUT || is_scanout) {
@@ -307,8 +306,8 @@ static int si_init_surface(struct si_screen *sscreen,
 	if (!(ptex->flags & SI_RESOURCE_FLAG_FORCE_TILING))
 		flags |= RADEON_SURF_OPTIMIZE_FOR_SPACE;
 
-	r = sscreen->ws->surface_init(sscreen->ws, ptex, num_color_samples,
-				      flags, bpe, array_mode, surface);
+	r = sscreen->ws->surface_init(sscreen->ws, ptex, flags, bpe,
+				      array_mode, surface);
 	if (r) {
 		return r;
 	}
@@ -1114,7 +1113,6 @@ void si_print_texture_info(struct si_screen *sscreen,
 static struct si_texture *
 si_texture_create_object(struct pipe_screen *screen,
 			 const struct pipe_resource *base,
-			 unsigned num_color_samples,
 			 struct pb_buffer *buf,
 			 struct radeon_surf *surface)
 {
@@ -1138,7 +1136,6 @@ si_texture_create_object(struct pipe_screen *screen,
 
 	tex->surface = *surface;
 	tex->size = tex->surface.surf_size;
-	tex->num_color_samples = num_color_samples;
 
 	tex->tc_compatible_htile = tex->surface.htile_size != 0 &&
 				   (tex->surface.flags &
@@ -1358,17 +1355,6 @@ si_choose_tiling(struct si_screen *sscreen,
 	return RADEON_SURF_MODE_2D;
 }
 
-static unsigned si_get_num_color_samples(struct si_screen *sscreen,
-					 const struct pipe_resource *templ,
-					 bool imported)
-{
-	if (!imported && templ->nr_samples >= 2 &&
-	    sscreen->eqaa_force_color_samples)
-		return sscreen->eqaa_force_color_samples;
-
-	return CLAMP(templ->nr_samples, 1, 8);
-}
-
 struct pipe_resource *si_texture_create(struct pipe_screen *screen,
 					const struct pipe_resource *templ)
 {
@@ -1382,10 +1368,13 @@ struct pipe_resource *si_texture_create(struct pipe_screen *screen,
 		 */
 		if (is_zs && sscreen->eqaa_force_z_samples) {
 			((struct pipe_resource*)templ)->nr_samples =
+			((struct pipe_resource*)templ)->nr_storage_samples =
 				sscreen->eqaa_force_z_samples;
 		} else if (!is_zs && sscreen->eqaa_force_color_samples) {
 			((struct pipe_resource*)templ)->nr_samples =
 				sscreen->eqaa_force_coverage_samples;
+			((struct pipe_resource*)templ)->nr_storage_samples =
+				sscreen->eqaa_force_color_samples;
 		}
 	}
 
@@ -1405,10 +1394,9 @@ struct pipe_resource *si_texture_create(struct pipe_screen *screen,
 		!is_flushed_depth &&
 		templ->nr_samples <= 1 && /* TC-compat HTILE is less efficient with MSAA */
 		is_zs;
-	unsigned num_color_samples = si_get_num_color_samples(sscreen, templ, false);
 	int r;
 
-	r = si_init_surface(sscreen, &surface, templ, num_color_samples,
+	r = si_init_surface(sscreen, &surface, templ,
 			    si_choose_tiling(sscreen, templ, tc_compatible_htile),
 			    0, 0, false, false, is_flushed_depth,
 			    tc_compatible_htile);
@@ -1417,8 +1405,7 @@ struct pipe_resource *si_texture_create(struct pipe_screen *screen,
 	}
 
 	return (struct pipe_resource *)
-	       si_texture_create_object(screen, templ, num_color_samples,
-					NULL, &surface);
+	       si_texture_create_object(screen, templ, NULL, &surface);
 }
 
 static struct pipe_resource *si_texture_from_winsys_buffer(struct si_screen *sscreen,
@@ -1467,16 +1454,13 @@ static struct pipe_resource *si_texture_from_winsys_buffer(struct si_screen *ssc
 		is_scanout = false;
 	}
 
-	unsigned num_color_samples = si_get_num_color_samples(sscreen, templ, true);
-
-	r = si_init_surface(sscreen, &surface, templ, num_color_samples,
+	r = si_init_surface(sscreen, &surface, templ,
 			    array_mode, stride, offset, true, is_scanout,
 			    false, false);
 	if (r)
 		return NULL;
 
-	tex = si_texture_create_object(&sscreen->b, templ, num_color_samples,
-				       buf, &surface);
+	tex = si_texture_create_object(&sscreen->b, templ, buf, &surface);
 	if (!tex)
 		return NULL;