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authorBas Nieuwenhuizen <[email protected]>2016-03-19 15:16:50 +0100
committerBas Nieuwenhuizen <[email protected]>2016-04-19 18:31:23 +0200
commit464cef5b06e65aa740704e4adac68b7f5fee1b88 (patch)
tree875b7715cf4db7bd7ab224213f9e34022a4b3bed /src/gallium/drivers/radeonsi
parent1f32d5d59fff7a4ef42cd2811ef4116c5827b9a0 (diff)
radeonsi: enable TGSI support cap for compute shaders
v2: Use chip_class instead of family. v3: Check kernel version for SI. v4: Preemptively allow amdgpu winsys for SI. Signed-off-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
Diffstat (limited to 'src/gallium/drivers/radeonsi')
-rw-r--r--src/gallium/drivers/radeonsi/si_pipe.c16
1 files changed, 14 insertions, 2 deletions
diff --git a/src/gallium/drivers/radeonsi/si_pipe.c b/src/gallium/drivers/radeonsi/si_pipe.c
index dabd28a4bc2..17d59b60d06 100644
--- a/src/gallium/drivers/radeonsi/si_pipe.c
+++ b/src/gallium/drivers/radeonsi/si_pipe.c
@@ -473,6 +473,8 @@ static int si_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
static int si_get_shader_param(struct pipe_screen* pscreen, unsigned shader, enum pipe_shader_cap param)
{
+ struct si_screen *sscreen = (struct si_screen *)pscreen;
+
switch(shader)
{
case PIPE_SHADER_FRAGMENT:
@@ -490,9 +492,19 @@ static int si_get_shader_param(struct pipe_screen* pscreen, unsigned shader, enu
case PIPE_SHADER_CAP_PREFERRED_IR:
return PIPE_SHADER_IR_NATIVE;
- case PIPE_SHADER_CAP_SUPPORTED_IRS:
- return 0;
+ case PIPE_SHADER_CAP_SUPPORTED_IRS: {
+ int ir = 1 << PIPE_SHADER_IR_NATIVE;
+ /* Old kernels disallowed some register writes for SI
+ * that are used for indirect dispatches. */
+ if (HAVE_LLVM >= 0x309 && (sscreen->b.chip_class >= CIK ||
+ sscreen->b.info.drm_major == 3 ||
+ (sscreen->b.info.drm_major == 2 &&
+ sscreen->b.info.drm_minor >= 45)))
+ ir |= 1 << PIPE_SHADER_IR_TGSI;
+
+ return ir;
+ }
case PIPE_SHADER_CAP_DOUBLES:
return HAVE_LLVM >= 0x0307;