diff options
author | Marek Olšák <[email protected]> | 2013-12-04 21:48:26 +0100 |
---|---|---|
committer | Marek Olšák <[email protected]> | 2013-12-12 18:48:04 +0100 |
commit | e4ef639a5700cff492fbddf7131d1cc9e52a2bb0 (patch) | |
tree | 19c5d05d7ef0169aad6499d22e3c8113ee5cbb46 /src/gallium/drivers/radeonsi | |
parent | 7fa8fb7382285797c34ef498da7a3a4cf3a85ebe (diff) |
r600g,radeonsi: fix initialized buffer range tracking for DMA, add comments
The DMA functions modify dst_offset and size and util_range_add gets wrong
values.
Reviewed-by: Michel Dänzer <[email protected]>
Diffstat (limited to 'src/gallium/drivers/radeonsi')
-rw-r--r-- | src/gallium/drivers/radeonsi/si_descriptors.c | 21 |
1 files changed, 12 insertions, 9 deletions
diff --git a/src/gallium/drivers/radeonsi/si_descriptors.c b/src/gallium/drivers/radeonsi/si_descriptors.c index e6d566d02e0..c43b35e3983 100644 --- a/src/gallium/drivers/radeonsi/si_descriptors.c +++ b/src/gallium/drivers/radeonsi/si_descriptors.c @@ -659,6 +659,12 @@ static void si_clear_buffer(struct pipe_context *ctx, struct pipe_resource *dst, if (!size) return; + /* Mark the buffer range of destination as valid (initialized), + * so that transfer_map knows it should wait for the GPU when mapping + * that range. */ + util_range_add(&r600_resource(dst)->valid_buffer_range, offset, + offset + size); + /* Fallback for unaligned clears. */ if (offset % 4 != 0 || size % 4 != 0) { uint32_t *map = rctx->b.ws->buffer_map(r600_resource(dst)->cs_buf, @@ -667,9 +673,6 @@ static void si_clear_buffer(struct pipe_context *ctx, struct pipe_resource *dst, size /= 4; for (unsigned i = 0; i < size; i++) *map++ = value; - - util_range_add(&r600_resource(dst)->valid_buffer_range, offset, - offset + size); return; } @@ -723,9 +726,6 @@ static void si_clear_buffer(struct pipe_context *ctx, struct pipe_resource *dst, R600_CONTEXT_FLUSH_AND_INV_DB | R600_CONTEXT_FLUSH_AND_INV_CB_META | R600_CONTEXT_FLUSH_AND_INV_DB_META; - - util_range_add(&r600_resource(dst)->valid_buffer_range, offset, - offset + size); } void si_copy_buffer(struct r600_context *rctx, @@ -735,6 +735,12 @@ void si_copy_buffer(struct r600_context *rctx, if (!size) return; + /* Mark the buffer range of destination as valid (initialized), + * so that transfer_map knows it should wait for the GPU when mapping + * that range. */ + util_range_add(&r600_resource(dst)->valid_buffer_range, dst_offset, + dst_offset + size); + dst_offset += r600_resource_va(&rctx->screen->b.b, dst); src_offset += r600_resource_va(&rctx->screen->b.b, src); @@ -781,9 +787,6 @@ void si_copy_buffer(struct r600_context *rctx, R600_CONTEXT_FLUSH_AND_INV_DB | R600_CONTEXT_FLUSH_AND_INV_CB_META | R600_CONTEXT_FLUSH_AND_INV_DB_META; - - util_range_add(&r600_resource(dst)->valid_buffer_range, dst_offset, - dst_offset + size); } /* INIT/DEINIT */ |