radeonsi: move definitions out of r600_pipe_common.h

Acked-by: Timothy Arceri <[email protected]>

9 files changed, 102 insertions, 26 deletions

diff --git a/src/gallium/drivers/radeonsi/si_blit.c b/src/gallium/drivers/radeonsi/si_blit.c
index c92fb2d7dbe..a88a5e22ca4 100644
--- a/src/gallium/drivers/radeonsi/si_blit.c
+++ b/src/gallium/drivers/radeonsi/si_blit.c
@@ -1174,8 +1174,8 @@ resolve_to_temp:
 	templ.depth0 = 1;
 	templ.array_size = 1;
 	templ.usage = PIPE_USAGE_DEFAULT;
-	templ.flags = R600_RESOURCE_FLAG_FORCE_TILING |
-		      R600_RESOURCE_FLAG_DISABLE_DCC;
+	templ.flags = SI_RESOURCE_FLAG_FORCE_TILING |
+		      SI_RESOURCE_FLAG_DISABLE_DCC;
 
 	/* The src and dst microtile modes must be the same. */
 	if (src->surface.micro_tile_mode == RADEON_MICRO_MODE_DISPLAY)
diff --git a/src/gallium/drivers/radeonsi/si_clear.c b/src/gallium/drivers/radeonsi/si_clear.c
index 403480cfb5f..9ae2a07343a 100644
--- a/src/gallium/drivers/radeonsi/si_clear.c
+++ b/src/gallium/drivers/radeonsi/si_clear.c
@@ -48,7 +48,7 @@ static void si_alloc_separate_cmask(struct si_screen *sscreen,
 
 	rtex->cmask_buffer = (struct r600_resource *)
 		si_aligned_buffer_create(&sscreen->b,
-					 R600_RESOURCE_FLAG_UNMAPPABLE,
+					 SI_RESOURCE_FLAG_UNMAPPABLE,
 					 PIPE_USAGE_DEFAULT,
 					 rtex->cmask.size,
 					 rtex->cmask.alignment);
diff --git a/src/gallium/drivers/radeonsi/si_compute.c b/src/gallium/drivers/radeonsi/si_compute.c
index 39579b2bb95..8c0d80fa043 100644
--- a/src/gallium/drivers/radeonsi/si_compute.c
+++ b/src/gallium/drivers/radeonsi/si_compute.c
@@ -360,7 +360,7 @@ static bool si_setup_compute_scratch_buffer(struct si_context *sctx,
 
 		sctx->compute_scratch_buffer = (struct r600_resource*)
 			si_aligned_buffer_create(&sctx->screen->b,
-						   R600_RESOURCE_FLAG_UNMAPPABLE,
+						   SI_RESOURCE_FLAG_UNMAPPABLE,
 						   PIPE_USAGE_DEFAULT,
 						   scratch_needed, 256);
 
diff --git a/src/gallium/drivers/radeonsi/si_cp_dma.c b/src/gallium/drivers/radeonsi/si_cp_dma.c
index b82e0abc529..7ce931a1d24 100644
--- a/src/gallium/drivers/radeonsi/si_cp_dma.c
+++ b/src/gallium/drivers/radeonsi/si_cp_dma.c
@@ -373,7 +373,7 @@ static void si_cp_dma_realign_engine(struct si_context *sctx, unsigned size,
 		r600_resource_reference(&sctx->scratch_buffer, NULL);
 		sctx->scratch_buffer = (struct r600_resource*)
 			si_aligned_buffer_create(&sctx->screen->b,
-						   R600_RESOURCE_FLAG_UNMAPPABLE,
+						   SI_RESOURCE_FLAG_UNMAPPABLE,
 						   PIPE_USAGE_DEFAULT,
 						   scratch_size, 256);
 		if (!sctx->scratch_buffer)
diff --git a/src/gallium/drivers/radeonsi/si_get.c b/src/gallium/drivers/radeonsi/si_get.c
index fb821e8da61..85cfb113383 100644
--- a/src/gallium/drivers/radeonsi/si_get.c
+++ b/src/gallium/drivers/radeonsi/si_get.c
@@ -214,7 +214,7 @@ static int si_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
 		       sscreen->info.drm_major == 3;
 
         case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
-                return R600_MAP_BUFFER_ALIGNMENT;
+                return SI_MAP_BUFFER_ALIGNMENT;
 
 	case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 	case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
@@ -282,7 +282,7 @@ static int si_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
 		return sscreen->info.has_syncobj;
 
 	case PIPE_CAP_CONSTBUF0_FLAGS:
-		return R600_RESOURCE_FLAG_32BIT;
+		return SI_RESOURCE_FLAG_32BIT;
 
 	case PIPE_CAP_NATIVE_FENCE_FD:
 		return sscreen->info.has_fence_to_handle;
diff --git a/src/gallium/drivers/radeonsi/si_pipe.c b/src/gallium/drivers/radeonsi/si_pipe.c
index d230d28dd55..298391127dd 100644
--- a/src/gallium/drivers/radeonsi/si_pipe.c
+++ b/src/gallium/drivers/radeonsi/si_pipe.c
@@ -383,15 +383,15 @@ static struct pipe_context *si_create_context(struct pipe_screen *screen,
 
 	sctx->b.b.stream_uploader = u_upload_create(&sctx->b.b, 1024 * 1024,
 						    0, PIPE_USAGE_STREAM,
-						    R600_RESOURCE_FLAG_READ_ONLY);
+						    SI_RESOURCE_FLAG_READ_ONLY);
 	if (!sctx->b.b.stream_uploader)
 		goto fail;
 
 	sctx->b.b.const_uploader = u_upload_create(&sctx->b.b, 128 * 1024,
 						   0, PIPE_USAGE_DEFAULT,
-						   R600_RESOURCE_FLAG_32BIT |
+						   SI_RESOURCE_FLAG_32BIT |
 						   (sscreen->cpdma_prefetch_writes_memory ?
-							    0 : R600_RESOURCE_FLAG_READ_ONLY));
+							    0 : SI_RESOURCE_FLAG_READ_ONLY));
 	if (!sctx->b.b.const_uploader)
 		goto fail;
 
@@ -500,7 +500,7 @@ static struct pipe_context *si_create_context(struct pipe_screen *screen,
 	if (sctx->b.chip_class == CIK) {
 		sctx->null_const_buf.buffer =
 			si_aligned_buffer_create(screen,
-						 R600_RESOURCE_FLAG_32BIT,
+						 SI_RESOURCE_FLAG_32BIT,
 						   PIPE_USAGE_DEFAULT, 16,
 						   sctx->screen->info.tcc_cache_line_size);
 		if (!sctx->null_const_buf.buffer)
diff --git a/src/gallium/drivers/radeonsi/si_pipe.h b/src/gallium/drivers/radeonsi/si_pipe.h
index 952a7a2a373..edfc5fa2ed5 100644
--- a/src/gallium/drivers/radeonsi/si_pipe.h
+++ b/src/gallium/drivers/radeonsi/si_pipe.h
@@ -36,19 +36,19 @@
 #define SI_BIG_ENDIAN 0
 #endif
 
-#define ATI_VENDOR_ID 0x1002
+#define ATI_VENDOR_ID			0x1002
 
-#define SI_NOT_QUERY		0xffffffff
+#define SI_NOT_QUERY			0xffffffff
 
 /* The base vertex and primitive restart can be any number, but we must pick
  * one which will mean "unknown" for the purpose of state tracking and
  * the number shouldn't be a commonly-used one. */
-#define SI_BASE_VERTEX_UNKNOWN INT_MIN
-#define SI_RESTART_INDEX_UNKNOWN INT_MIN
-#define SI_NUM_SMOOTH_AA_SAMPLES 8
-#define SI_GS_PER_ES 128
+#define SI_BASE_VERTEX_UNKNOWN		INT_MIN
+#define SI_RESTART_INDEX_UNKNOWN	INT_MIN
+#define SI_NUM_SMOOTH_AA_SAMPLES	8
+#define SI_GS_PER_ES			128
 /* Alignment for optimal CP DMA performance. */
-#define SI_CPDMA_ALIGNMENT	32
+#define SI_CPDMA_ALIGNMENT		32
 
 /* Pipeline & streamout query controls. */
 #define SI_CONTEXT_START_PIPELINE_STATS	(1 << 0)
@@ -87,9 +87,85 @@
 #define SI_PREFETCH_VS			(1 << 5)
 #define SI_PREFETCH_PS			(1 << 6)
 
-#define SI_MAX_BORDER_COLORS	4096
-#define SI_MAX_VIEWPORTS        16
-#define SIX_BITS		0x3F
+#define SI_MAX_BORDER_COLORS		4096
+#define SI_MAX_VIEWPORTS		16
+#define SIX_BITS			0x3F
+#define SI_MAP_BUFFER_ALIGNMENT		64
+#define SI_MAX_VARIABLE_THREADS_PER_BLOCK 1024
+
+#define SI_RESOURCE_FLAG_TRANSFER	(PIPE_RESOURCE_FLAG_DRV_PRIV << 0)
+#define SI_RESOURCE_FLAG_FLUSHED_DEPTH	(PIPE_RESOURCE_FLAG_DRV_PRIV << 1)
+#define SI_RESOURCE_FLAG_FORCE_TILING	(PIPE_RESOURCE_FLAG_DRV_PRIV << 2)
+#define SI_RESOURCE_FLAG_DISABLE_DCC	(PIPE_RESOURCE_FLAG_DRV_PRIV << 3)
+#define SI_RESOURCE_FLAG_UNMAPPABLE	(PIPE_RESOURCE_FLAG_DRV_PRIV << 4)
+#define SI_RESOURCE_FLAG_READ_ONLY	(PIPE_RESOURCE_FLAG_DRV_PRIV << 5)
+#define SI_RESOURCE_FLAG_32BIT		(PIPE_RESOURCE_FLAG_DRV_PRIV << 6)
+
+/* Debug flags. */
+enum {
+	/* Shader logging options: */
+	DBG_VS = PIPE_SHADER_VERTEX,
+	DBG_PS = PIPE_SHADER_FRAGMENT,
+	DBG_GS = PIPE_SHADER_GEOMETRY,
+	DBG_TCS = PIPE_SHADER_TESS_CTRL,
+	DBG_TES = PIPE_SHADER_TESS_EVAL,
+	DBG_CS = PIPE_SHADER_COMPUTE,
+	DBG_NO_IR,
+	DBG_NO_TGSI,
+	DBG_NO_ASM,
+	DBG_PREOPT_IR,
+
+	/* Shader compiler options the shader cache should be aware of: */
+	DBG_FS_CORRECT_DERIVS_AFTER_KILL,
+	DBG_UNSAFE_MATH,
+	DBG_SI_SCHED,
+
+	/* Shader compiler options (with no effect on the shader cache): */
+	DBG_CHECK_IR,
+	DBG_NIR,
+	DBG_MONOLITHIC_SHADERS,
+	DBG_NO_OPT_VARIANT,
+
+	/* Information logging options: */
+	DBG_INFO,
+	DBG_TEX,
+	DBG_COMPUTE,
+	DBG_VM,
+
+	/* Driver options: */
+	DBG_FORCE_DMA,
+	DBG_NO_ASYNC_DMA,
+	DBG_NO_WC,
+	DBG_CHECK_VM,
+	DBG_RESERVE_VMID,
+
+	/* 3D engine options: */
+	DBG_SWITCH_ON_EOP,
+	DBG_NO_OUT_OF_ORDER,
+	DBG_NO_DPBB,
+	DBG_NO_DFSM,
+	DBG_DPBB,
+	DBG_DFSM,
+	DBG_NO_HYPERZ,
+	DBG_NO_RB_PLUS,
+	DBG_NO_2D_TILING,
+	DBG_NO_TILING,
+	DBG_NO_DCC,
+	DBG_NO_DCC_CLEAR,
+	DBG_NO_DCC_FB,
+	DBG_NO_DCC_MSAA,
+	DBG_DCC_MSAA,
+	DBG_NO_FMASK,
+
+	/* Tests: */
+	DBG_TEST_DMA,
+	DBG_TEST_VMFAULT_CP,
+	DBG_TEST_VMFAULT_SDMA,
+	DBG_TEST_VMFAULT_SHADER,
+};
+
+#define DBG_ALL_SHADERS		(((1 << (DBG_CS + 1)) - 1))
+#define DBG(name)		(1ull << DBG_##name)
 
 struct si_compute;
 struct hash_table;
diff --git a/src/gallium/drivers/radeonsi/si_shader.c b/src/gallium/drivers/radeonsi/si_shader.c
index 5ec6f3fc301..c18915488e5 100644
--- a/src/gallium/drivers/radeonsi/si_shader.c
+++ b/src/gallium/drivers/radeonsi/si_shader.c
@@ -5350,7 +5350,7 @@ int si_shader_binary_upload(struct si_screen *sscreen, struct si_shader *shader)
 	shader->bo = (struct r600_resource*)
 		     si_aligned_buffer_create(&sscreen->b,
 					      sscreen->cpdma_prefetch_writes_memory ?
-						0 : R600_RESOURCE_FLAG_READ_ONLY,
+						0 : SI_RESOURCE_FLAG_READ_ONLY,
                                               PIPE_USAGE_IMMUTABLE,
                                               align(bo_size, SI_CPDMA_ALIGNMENT),
                                               256);
diff --git a/src/gallium/drivers/radeonsi/si_state_shaders.c b/src/gallium/drivers/radeonsi/si_state_shaders.c
index 6043de2c6e8..b6a618ddd59 100644
--- a/src/gallium/drivers/radeonsi/si_state_shaders.c
+++ b/src/gallium/drivers/radeonsi/si_state_shaders.c
@@ -2723,7 +2723,7 @@ static bool si_update_gs_ring_buffers(struct si_context *sctx)
 		pipe_resource_reference(&sctx->esgs_ring, NULL);
 		sctx->esgs_ring =
 			si_aligned_buffer_create(sctx->b.b.screen,
-						   R600_RESOURCE_FLAG_UNMAPPABLE,
+						   SI_RESOURCE_FLAG_UNMAPPABLE,
 						   PIPE_USAGE_DEFAULT,
 						   esgs_ring_size, alignment);
 		if (!sctx->esgs_ring)
@@ -2734,7 +2734,7 @@ static bool si_update_gs_ring_buffers(struct si_context *sctx)
 		pipe_resource_reference(&sctx->gsvs_ring, NULL);
 		sctx->gsvs_ring =
 			si_aligned_buffer_create(sctx->b.b.screen,
-						   R600_RESOURCE_FLAG_UNMAPPABLE,
+						   SI_RESOURCE_FLAG_UNMAPPABLE,
 						   PIPE_USAGE_DEFAULT,
 						   gsvs_ring_size, alignment);
 		if (!sctx->gsvs_ring)
@@ -2976,7 +2976,7 @@ static bool si_update_spi_tmpring_size(struct si_context *sctx)
 
 			sctx->scratch_buffer = (struct r600_resource*)
 				si_aligned_buffer_create(&sctx->screen->b,
-							   R600_RESOURCE_FLAG_UNMAPPABLE,
+							   SI_RESOURCE_FLAG_UNMAPPABLE,
 							   PIPE_USAGE_DEFAULT,
 							   scratch_needed_size, 256);
 			if (!sctx->scratch_buffer)
@@ -3012,7 +3012,7 @@ static void si_init_tess_factor_ring(struct si_context *sctx)
 	 * receives the high 13 bits.
 	 */
 	sctx->tess_rings = si_aligned_buffer_create(sctx->b.b.screen,
-						    R600_RESOURCE_FLAG_32BIT,
+						    SI_RESOURCE_FLAG_32BIT,
 						    PIPE_USAGE_DEFAULT,
 						    sctx->screen->tess_offchip_ring_size +
 						    sctx->screen->tess_factor_ring_size,