gallium/radeon: drop support for LINEAR_GENERAL layout

Unused. All texture imports use LINEAR_ALIGNED regardless of what
the DDX does.

Reviewed-by: Alex Deucher <[email protected]>

3 files changed, 7 insertions, 31 deletions

diff --git a/src/gallium/drivers/radeonsi/cik_sdma.c b/src/gallium/drivers/radeonsi/cik_sdma.c
index 6eb62dcc890..07a7d945301 100644
--- a/src/gallium/drivers/radeonsi/cik_sdma.c
+++ b/src/gallium/drivers/radeonsi/cik_sdma.c
@@ -126,17 +126,14 @@ static void cik_sdma_copy_tile(struct si_context *ctx,
 
 	dst_mode = rdst->surface.level[dst_level].mode;
 	src_mode = rsrc->surface.level[src_level].mode;
-	/* downcast linear aligned to linear to simplify test */
-	src_mode = src_mode == RADEON_SURF_MODE_LINEAR_ALIGNED ? RADEON_SURF_MODE_LINEAR : src_mode;
-	dst_mode = dst_mode == RADEON_SURF_MODE_LINEAR_ALIGNED ? RADEON_SURF_MODE_LINEAR : dst_mode;
 	assert(dst_mode != src_mode);
-	assert(src_mode == RADEON_SURF_MODE_LINEAR || dst_mode == RADEON_SURF_MODE_LINEAR);
+	assert(src_mode == RADEON_SURF_MODE_LINEAR_ALIGNED || dst_mode == RADEON_SURF_MODE_LINEAR_ALIGNED);
 
 	sub_op = CIK_SDMA_COPY_SUB_OPCODE_TILED;
 	lbpe = util_logbase2(bpe);
 	pitch_tile_max = ((pitch / bpe) / 8) - 1;
 
-	detile = dst_mode == RADEON_SURF_MODE_LINEAR;
+	detile = dst_mode == RADEON_SURF_MODE_LINEAR_ALIGNED;
 	rlinear = detile ? rdst : rsrc;
 	rtiled = detile ? rsrc : rdst;
 	linear_lvl = detile ? dst_level : src_level;
@@ -276,12 +273,9 @@ void cik_sdma_copy(struct pipe_context *ctx,
 	copy_height = src_box->height / rsrc->surface.blk_h;
 	dst_mode = rdst->surface.level[dst_level].mode;
 	src_mode = rsrc->surface.level[src_level].mode;
-	/* downcast linear aligned to linear to simplify test */
-	src_mode = src_mode == RADEON_SURF_MODE_LINEAR_ALIGNED ? RADEON_SURF_MODE_LINEAR : src_mode;
-	dst_mode = dst_mode == RADEON_SURF_MODE_LINEAR_ALIGNED ? RADEON_SURF_MODE_LINEAR : dst_mode;
 
 	/* Dimensions must be aligned to (macro)tiles */
-	switch (src_mode == RADEON_SURF_MODE_LINEAR ? dst_mode : src_mode) {
+	switch (src_mode == RADEON_SURF_MODE_LINEAR_ALIGNED ? dst_mode : src_mode) {
 	case RADEON_SURF_MODE_1D:
 		if ((src_x % 8) || (src_y % 8) || (dst_x % 8) || (dst_y % 8) ||
 		    (copy_height % 8))
diff --git a/src/gallium/drivers/radeonsi/si_dma.c b/src/gallium/drivers/radeonsi/si_dma.c
index 0efca193951..688edbe601f 100644
--- a/src/gallium/drivers/radeonsi/si_dma.c
+++ b/src/gallium/drivers/radeonsi/si_dma.c
@@ -126,16 +126,13 @@ static void si_dma_copy_tile(struct si_context *ctx,
 
 	dst_mode = rdst->surface.level[dst_level].mode;
 	src_mode = rsrc->surface.level[src_level].mode;
-	/* downcast linear aligned to linear to simplify test */
-	src_mode = src_mode == RADEON_SURF_MODE_LINEAR_ALIGNED ? RADEON_SURF_MODE_LINEAR : src_mode;
-	dst_mode = dst_mode == RADEON_SURF_MODE_LINEAR_ALIGNED ? RADEON_SURF_MODE_LINEAR : dst_mode;
 	assert(dst_mode != src_mode);
 
 	sub_cmd = SI_DMA_COPY_TILED;
 	lbpp = util_logbase2(bpp);
 	pitch_tile_max = ((pitch / bpp) / 8) - 1;
 
-	detile = dst_mode == RADEON_SURF_MODE_LINEAR;
+	detile = dst_mode == RADEON_SURF_MODE_LINEAR_ALIGNED;
 	rlinear = detile ? rdst : rsrc;
 	rtiled = detile ? rsrc : rdst;
 	linear_lvl = detile ? dst_level : src_level;
@@ -270,9 +267,6 @@ void si_dma_copy(struct pipe_context *ctx,
 
 	dst_mode = rdst->surface.level[dst_level].mode;
 	src_mode = rsrc->surface.level[src_level].mode;
-	/* downcast linear aligned to linear to simplify test */
-	src_mode = src_mode == RADEON_SURF_MODE_LINEAR_ALIGNED ? RADEON_SURF_MODE_LINEAR : src_mode;
-	dst_mode = dst_mode == RADEON_SURF_MODE_LINEAR_ALIGNED ? RADEON_SURF_MODE_LINEAR : dst_mode;
 
 	if (src_pitch != dst_pitch || src_box->x || dst_x || src_w != dst_w ||
 	    src_box->width != src_w ||
diff --git a/src/gallium/drivers/radeonsi/si_state.c b/src/gallium/drivers/radeonsi/si_state.c
index c214932e28b..1dd468b596d 100644
--- a/src/gallium/drivers/radeonsi/si_state.c
+++ b/src/gallium/drivers/radeonsi/si_state.c
@@ -58,15 +58,13 @@ void si_init_atom(struct si_context *sctx, struct r600_atom *atom,
 unsigned si_array_mode(unsigned mode)
 {
 	switch (mode) {
+	default:
 	case RADEON_SURF_MODE_LINEAR_ALIGNED:
 		return V_009910_ARRAY_LINEAR_ALIGNED;
 	case RADEON_SURF_MODE_1D:
 		return V_009910_ARRAY_1D_TILED_THIN1;
 	case RADEON_SURF_MODE_2D:
 		return V_009910_ARRAY_2D_TILED_THIN1;
-	default:
-	case RADEON_SURF_MODE_LINEAR:
-		return V_009910_ARRAY_LINEAR_GENERAL;
 	}
 }
 
@@ -2119,17 +2117,8 @@ static void si_initialize_color_surface(struct si_context *sctx,
 	int i;
 	unsigned blend_clamp = 0, blend_bypass = 0;
 
-	/* Layered rendering doesn't work with LINEAR_GENERAL.
-	 * (LINEAR_ALIGNED and others work) */
-	if (rtex->surface.level[level].mode == RADEON_SURF_MODE_LINEAR) {
-		assert(surf->base.u.tex.first_layer == surf->base.u.tex.last_layer);
-		offset += rtex->surface.level[level].slice_size *
-			  surf->base.u.tex.first_layer;
-		color_view = 0;
-	} else {
-		color_view = S_028C6C_SLICE_START(surf->base.u.tex.first_layer) |
-			     S_028C6C_SLICE_MAX(surf->base.u.tex.last_layer);
-	}
+	color_view = S_028C6C_SLICE_START(surf->base.u.tex.first_layer) |
+		     S_028C6C_SLICE_MAX(surf->base.u.tex.last_layer);
 
 	pitch = (rtex->surface.level[level].nblk_x) / 8 - 1;
 	slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64;
@@ -2346,7 +2335,6 @@ static void si_init_depth_surface(struct si_context *sctx,
 			break;
 		case RADEON_SURF_MODE_1D:
 		case RADEON_SURF_MODE_LINEAR_ALIGNED:
-		case RADEON_SURF_MODE_LINEAR:
 		default:
 			array_mode = V_02803C_ARRAY_1D_TILED_THIN1;
 			break;