diff options
| author | Marek Olšák <[email protected]> | 2019-01-17 14:45:10 -0500 |
|---|---|---|
| committer | Marek Olšák <[email protected]> | 2019-01-22 12:14:26 -0500 |
| commit | a545415eb9765f46e6f358657b15171d07f89842 (patch) | |
| tree | 643c7ec9e980652aeced7474833a97f17e8f351a /src/gallium/drivers/radeonsi | |
| parent | e402961e1dc49031c68a1373620abdaa3b9efbe6 (diff) | |
radeonsi: fix the top-of-pipe fence on SI
SI doesn't have MEM.
Reviewed-by: Bas Nieuwenhuizen <[email protected]>
Diffstat (limited to 'src/gallium/drivers/radeonsi')
| -rw-r--r-- | src/gallium/drivers/radeonsi/si_fence.c | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/src/gallium/drivers/radeonsi/si_fence.c b/src/gallium/drivers/radeonsi/si_fence.c index be394119af6..46d0289c90b 100644 --- a/src/gallium/drivers/radeonsi/si_fence.c +++ b/src/gallium/drivers/radeonsi/si_fence.c @@ -266,7 +266,8 @@ static void si_fine_fence_set(struct si_context *ctx, if (flags & PIPE_FLUSH_TOP_OF_PIPE) { struct radeon_cmdbuf *cs = ctx->gfx_cs; radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, 0)); - radeon_emit(cs, S_370_DST_SEL(V_370_MEM) | + radeon_emit(cs, S_370_DST_SEL(ctx->chip_class >= CIK ? V_370_MEM + : V_370_MEM_GRBM) | S_370_WR_CONFIRM(1) | S_370_ENGINE_SEL(V_370_PFP)); radeon_emit(cs, fence_va); |