radeonsi: rework clear_buffer flags

Changes:
- don't flush DB for fast color clears
- don't flush any caches for initial clears
- remove the flag from si_copy_buffer, always assume shader coherency

Reviewed-by: Nicolai Hähnle <[email protected]>

4 files changed, 28 insertions, 21 deletions

diff --git a/src/gallium/drivers/radeonsi/si_blit.c b/src/gallium/drivers/radeonsi/si_blit.c
index 6fa5b975d9d..0233e10c975 100644
--- a/src/gallium/drivers/radeonsi/si_blit.c
+++ b/src/gallium/drivers/radeonsi/si_blit.c
@@ -630,7 +630,7 @@ void si_resource_copy_region(struct pipe_context *ctx,
 
 	/* Handle buffers first. */
 	if (dst->target == PIPE_BUFFER && src->target == PIPE_BUFFER) {
-		si_copy_buffer(sctx, dst, src, dstx, src_box->x, src_box->width, false);
+		si_copy_buffer(sctx, dst, src, dstx, src_box->x, src_box->width);
 		return;
 	}
 
@@ -949,7 +949,8 @@ static void si_pipe_clear_buffer(struct pipe_context *ctx,
 		dword_value = *(uint32_t*)clear_value_ptr;
 	}
 
-	sctx->b.clear_buffer(ctx, dst, offset, size, dword_value, false);
+	sctx->b.clear_buffer(ctx, dst, offset, size, dword_value,
+			     R600_COHERENCY_SHADER);
 }
 
 void si_init_blit_functions(struct si_context *sctx)
diff --git a/src/gallium/drivers/radeonsi/si_cp_dma.c b/src/gallium/drivers/radeonsi/si_cp_dma.c
index bca9cc5020e..cbb84b00ce4 100644
--- a/src/gallium/drivers/radeonsi/si_cp_dma.c
+++ b/src/gallium/drivers/radeonsi/si_cp_dma.c
@@ -107,19 +107,26 @@ static void si_emit_cp_dma_clear_buffer(struct si_context *sctx,
 	}
 }
 
-static unsigned get_flush_flags(struct si_context *sctx, bool is_framebuffer)
+static unsigned get_flush_flags(struct si_context *sctx, enum r600_coherency coher)
 {
-	if (is_framebuffer)
-		return SI_CONTEXT_FLUSH_AND_INV_FRAMEBUFFER;
-
-	return SI_CONTEXT_INV_SMEM_L1 |
-	       SI_CONTEXT_INV_VMEM_L1 |
-	       (sctx->b.chip_class == SI ? SI_CONTEXT_INV_GLOBAL_L2 : 0);
+	switch (coher) {
+	default:
+	case R600_COHERENCY_NONE:
+		return 0;
+	case R600_COHERENCY_SHADER:
+		return SI_CONTEXT_INV_SMEM_L1 |
+		       SI_CONTEXT_INV_VMEM_L1 |
+		       (sctx->b.chip_class == SI ? SI_CONTEXT_INV_GLOBAL_L2 : 0);
+	case R600_COHERENCY_CB_META:
+		return SI_CONTEXT_FLUSH_AND_INV_CB |
+		       SI_CONTEXT_FLUSH_AND_INV_CB_META;
+	}
 }
 
-static unsigned get_tc_l2_flag(struct si_context *sctx, bool is_framebuffer)
+static unsigned get_tc_l2_flag(struct si_context *sctx, enum r600_coherency coher)
 {
-	return is_framebuffer || sctx->b.chip_class == SI ? 0 : CIK_CP_DMA_USE_L2;
+	return coher == R600_COHERENCY_SHADER &&
+	       sctx->b.chip_class >= CIK ? CIK_CP_DMA_USE_L2 : 0;
 }
 
 static void si_cp_dma_prepare(struct si_context *sctx, struct pipe_resource *dst,
@@ -159,11 +166,11 @@ static void si_cp_dma_prepare(struct si_context *sctx, struct pipe_resource *dst
 
 static void si_clear_buffer(struct pipe_context *ctx, struct pipe_resource *dst,
 			    uint64_t offset, uint64_t size, unsigned value,
-			    bool is_framebuffer)
+			    enum r600_coherency coher)
 {
 	struct si_context *sctx = (struct si_context*)ctx;
-	unsigned tc_l2_flag = get_tc_l2_flag(sctx, is_framebuffer);
-	unsigned flush_flags = get_flush_flags(sctx, is_framebuffer);
+	unsigned tc_l2_flag = get_tc_l2_flag(sctx, coher);
+	unsigned flush_flags = get_flush_flags(sctx, coher);
 
 	if (!size)
 		return;
@@ -249,14 +256,13 @@ static void si_cp_dma_realign_engine(struct si_context *sctx, unsigned size)
 
 void si_copy_buffer(struct si_context *sctx,
 		    struct pipe_resource *dst, struct pipe_resource *src,
-		    uint64_t dst_offset, uint64_t src_offset, unsigned size,
-		    bool is_framebuffer)
+		    uint64_t dst_offset, uint64_t src_offset, unsigned size)
 {
 	uint64_t main_dst_offset, main_src_offset;
 	unsigned skipped_size = 0;
 	unsigned realign_size = 0;
-	unsigned tc_l2_flag = get_tc_l2_flag(sctx, is_framebuffer);
-	unsigned flush_flags = get_flush_flags(sctx, is_framebuffer);
+	unsigned tc_l2_flag = get_tc_l2_flag(sctx, R600_COHERENCY_SHADER);
+	unsigned flush_flags = get_flush_flags(sctx, R600_COHERENCY_SHADER);
 
 	if (!size)
 		return;
diff --git a/src/gallium/drivers/radeonsi/si_pipe.c b/src/gallium/drivers/radeonsi/si_pipe.c
index ab6ea40ac93..61d55781161 100644
--- a/src/gallium/drivers/radeonsi/si_pipe.c
+++ b/src/gallium/drivers/radeonsi/si_pipe.c
@@ -224,7 +224,8 @@ static struct pipe_context *si_create_context(struct pipe_screen *screen,
 
 		/* Clear the NULL constant buffer, because loads should return zeros. */
 		sctx->b.clear_buffer(&sctx->b.b, sctx->null_const_buf.buffer, 0,
-				     sctx->null_const_buf.buffer->width0, 0, false);
+				     sctx->null_const_buf.buffer->width0, 0,
+				     R600_COHERENCY_SHADER);
 	}
 
 	/* XXX: This is the maximum value allowed.  I'm not sure how to compute
diff --git a/src/gallium/drivers/radeonsi/si_pipe.h b/src/gallium/drivers/radeonsi/si_pipe.h
index 13946a5ad71..d31e9a93ef9 100644
--- a/src/gallium/drivers/radeonsi/si_pipe.h
+++ b/src/gallium/drivers/radeonsi/si_pipe.h
@@ -348,8 +348,7 @@ void si_resource_copy_region(struct pipe_context *ctx,
 /* si_cp_dma.c */
 void si_copy_buffer(struct si_context *sctx,
 		    struct pipe_resource *dst, struct pipe_resource *src,
-		    uint64_t dst_offset, uint64_t src_offset, unsigned size,
-		    bool is_framebuffer);
+		    uint64_t dst_offset, uint64_t src_offset, unsigned size);
 void si_init_cp_dma_functions(struct si_context *sctx);
 
 /* si_debug.c */