radeonsi: move drawing into new state handling

Signed-off-by: Christian König <[email protected]>

4 files changed, 72 insertions, 103 deletions

diff --git a/src/gallium/drivers/radeonsi/evergreen_hw_context.c b/src/gallium/drivers/radeonsi/evergreen_hw_context.c
index 56b068fe063..44fc9500a2d 100644
--- a/src/gallium/drivers/radeonsi/evergreen_hw_context.c
+++ b/src/gallium/drivers/radeonsi/evergreen_hw_context.c
@@ -42,58 +42,4 @@ int si_context_init(struct r600_context *ctx)
 	return 0;
 }
 
-void si_context_draw(struct r600_context *ctx, const struct r600_draw *draw)
-{
-	struct radeon_winsys_cs *cs = ctx->cs;
-	unsigned ndwords = 7;
-	uint32_t *pm4;
-	uint64_t va;
-
-	if (draw->indices) {
-		ndwords = 12;
-	}
-	if (ctx->num_cs_dw_queries_suspend)
-		ndwords += 6;
-
-	/* when increasing ndwords, bump the max limit too */
-	assert(ndwords <= SI_MAX_DRAW_CS_DWORDS);
 
-	/* queries need some special values
-	 * (this is non-zero if any query is active) */
-	if (ctx->num_cs_dw_queries_suspend) {
-		pm4 = &cs->buf[cs->cdw];
-		pm4[0] = PKT3(PKT3_SET_CONTEXT_REG, 1, 0);
-		pm4[1] = (R_028004_DB_COUNT_CONTROL - SI_CONTEXT_REG_OFFSET) >> 2;
-		pm4[2] = S_028004_PERFECT_ZPASS_COUNTS(1);
-		pm4[3] = PKT3(PKT3_SET_CONTEXT_REG, 1, 0);
-		pm4[4] = (R_02800C_DB_RENDER_OVERRIDE - SI_CONTEXT_REG_OFFSET) >> 2;
-		pm4[5] = draw->db_render_override | S_02800C_NOOP_CULL_DISABLE(1);
-		cs->cdw += 6;
-		ndwords -= 6;
-	}
-
-	/* draw packet */
-	pm4 = &cs->buf[cs->cdw];
-	pm4[0] = PKT3(PKT3_INDEX_TYPE, 0, ctx->predicate_drawing);
-	pm4[1] = draw->vgt_index_type;
-	pm4[2] = PKT3(PKT3_NUM_INSTANCES, 0, ctx->predicate_drawing);
-	pm4[3] = draw->vgt_num_instances;
-	if (draw->indices) {
-		va = r600_resource_va(&ctx->screen->screen, (void*)draw->indices);
-		va += draw->indices_bo_offset;
-		pm4[4] = PKT3(PKT3_DRAW_INDEX_2, 4, ctx->predicate_drawing);
-		pm4[5] = (draw->indices->b.b.width0 - draw->indices_bo_offset) /
-			ctx->index_buffer.index_size;
-		pm4[6] = va;
-		pm4[7] = (va >> 32UL) & 0xFF;
-		pm4[8] = draw->vgt_num_indices;
-		pm4[9] = draw->vgt_draw_initiator;
-		pm4[10] = PKT3(PKT3_NOP, 0, ctx->predicate_drawing);
-		pm4[11] = r600_context_bo_reloc(ctx, draw->indices, RADEON_USAGE_READ);
-	} else {
-		pm4[4] = PKT3(PKT3_DRAW_INDEX_AUTO, 1, ctx->predicate_drawing);
-		pm4[5] = draw->vgt_num_indices;
-		pm4[6] = draw->vgt_draw_initiator;
-	}
-	cs->cdw += ndwords;
-}
diff --git a/src/gallium/drivers/radeonsi/r600.h b/src/gallium/drivers/radeonsi/r600.h
index f34d1ff5737..df9e7a08fae 100644
--- a/src/gallium/drivers/radeonsi/r600.h
+++ b/src/gallium/drivers/radeonsi/r600.h
@@ -95,17 +95,6 @@ struct r600_so_target {
 #define R600_CONTEXT_DST_CACHES_DIRTY	(1 << 1)
 #define R600_CONTEXT_CHECK_EVENT_FLUSH	(1 << 2)
 
-struct r600_draw {
-	uint32_t		vgt_num_indices;
-	uint32_t		vgt_num_instances;
-	uint32_t		vgt_index_type;
-	uint32_t		vgt_draw_initiator;
-	uint32_t		indices_bo_offset;
-	unsigned		db_render_override;
-	unsigned		db_render_control;
-	struct si_resource	*indices;
-};
-
 struct r600_context;
 struct r600_screen;
 
@@ -130,6 +119,5 @@ void r600_context_draw_opaque_count(struct r600_context *ctx, struct r600_so_tar
 void r600_need_cs_space(struct r600_context *ctx, unsigned num_dw, boolean count_draw_in);
 
 int si_context_init(struct r600_context *ctx);
-void si_context_draw(struct r600_context *ctx, const struct r600_draw *draw);
 
 #endif
diff --git a/src/gallium/drivers/radeonsi/si_state.h b/src/gallium/drivers/radeonsi/si_state.h
index 475432d54fb..87b53702314 100644
--- a/src/gallium/drivers/radeonsi/si_state.h
+++ b/src/gallium/drivers/radeonsi/si_state.h
@@ -93,6 +93,7 @@ union si_state {
 		struct si_pm4_state		*vertex_buffers;
 		struct si_pm4_state		*texture_barrier;
 		struct si_pm4_state		*draw_info;
+		struct si_pm4_state		*draw;
 	} named;
 	struct si_pm4_state	*array[0];
 };
diff --git a/src/gallium/drivers/radeonsi/si_state_draw.c b/src/gallium/drivers/radeonsi/si_state_draw.c
index e3573697d95..43644e591ed 100644
--- a/src/gallium/drivers/radeonsi/si_state_draw.c
+++ b/src/gallium/drivers/radeonsi/si_state_draw.c
@@ -251,7 +251,8 @@ static bool si_update_draw_info_state(struct r600_context *rctx,
 	si_pm4_set_reg(pm4, R_008958_VGT_PRIMITIVE_TYPE, prim);
 	si_pm4_set_reg(pm4, R_028400_VGT_MAX_VTX_INDX, ~0);
 	si_pm4_set_reg(pm4, R_028404_VGT_MIN_VTX_INDX, 0);
-	si_pm4_set_reg(pm4, R_028408_VGT_INDX_OFFSET, info->index_bias);
+	si_pm4_set_reg(pm4, R_028408_VGT_INDX_OFFSET,
+		       info->indexed ? info->index_bias : info->start);
 	si_pm4_set_reg(pm4, R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX, info->restart_index);
 	si_pm4_set_reg(pm4, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN, info->primitive_restart);
 #if 0
@@ -459,17 +460,72 @@ static void si_vertex_buffer_update(struct r600_context *rctx)
 	si_pm4_set_state(rctx, vertex_buffers, pm4);
 }
 
-void si_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *dinfo)
+static void si_state_draw(struct r600_context *rctx,
+			  const struct pipe_draw_info *info,
+			  const struct pipe_index_buffer *ib)
+{
+	struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
+
+	/* queries need some special values
+	 * (this is non-zero if any query is active) */
+	if (rctx->num_cs_dw_queries_suspend) {
+		struct si_state_dsa *dsa = rctx->queued.named.dsa;
+
+		si_pm4_set_reg(pm4, R_028004_DB_COUNT_CONTROL,
+			       S_028004_PERFECT_ZPASS_COUNTS(1));
+		si_pm4_set_reg(pm4, R_02800C_DB_RENDER_OVERRIDE,
+			       dsa->db_render_override |
+			       S_02800C_NOOP_CULL_DISABLE(1));
+	}
+
+	/* draw packet */
+	si_pm4_cmd_begin(pm4, PKT3_INDEX_TYPE);
+	if (ib->index_size == 4) {
+		si_pm4_cmd_add(pm4, V_028A7C_VGT_INDEX_32 | (R600_BIG_ENDIAN ?
+				V_028A7C_VGT_DMA_SWAP_32_BIT : 0));
+	} else {
+		si_pm4_cmd_add(pm4, V_028A7C_VGT_INDEX_16 | (R600_BIG_ENDIAN ?
+				V_028A7C_VGT_DMA_SWAP_16_BIT : 0));
+	}
+	si_pm4_cmd_end(pm4, rctx->predicate_drawing);
+
+	si_pm4_cmd_begin(pm4, PKT3_NUM_INSTANCES);
+	si_pm4_cmd_add(pm4, info->instance_count);
+	si_pm4_cmd_end(pm4, rctx->predicate_drawing);
+
+	if (info->indexed) {
+		uint64_t va;
+		va = r600_resource_va(&rctx->screen->screen, ib->buffer);
+		va += ib->offset;
+
+		si_pm4_add_bo(pm4, (struct si_resource *)ib->buffer, RADEON_USAGE_READ);
+		si_pm4_cmd_begin(pm4, PKT3_DRAW_INDEX_2);
+		si_pm4_cmd_add(pm4, (ib->buffer->width0 - ib->offset) /
+					rctx->index_buffer.index_size);
+		si_pm4_cmd_add(pm4, va);
+		si_pm4_cmd_add(pm4, (va >> 32UL) & 0xFF);
+		si_pm4_cmd_add(pm4, info->count);
+		si_pm4_cmd_add(pm4, V_0287F0_DI_SRC_SEL_DMA);
+		si_pm4_cmd_end(pm4, rctx->predicate_drawing);
+	} else {
+		si_pm4_cmd_begin(pm4, PKT3_DRAW_INDEX_AUTO);
+		si_pm4_cmd_add(pm4, info->count);
+		si_pm4_cmd_add(pm4, V_0287F0_DI_SRC_SEL_AUTO_INDEX |
+			       (info->count_from_stream_output ?
+				S_0287F0_USE_OPAQUE(1) : 0));
+		si_pm4_cmd_end(pm4, rctx->predicate_drawing);
+	}
+	si_pm4_set_state(rctx, draw, pm4);
+}
+
+void si_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info)
 {
 	struct r600_context *rctx = (struct r600_context *)ctx;
-	struct si_state_dsa *dsa = rctx->queued.named.dsa;
-	struct pipe_draw_info info = *dinfo;
-	struct r600_draw rdraw = {};
 	struct pipe_index_buffer ib = {};
 	uint32_t cp_coher_cntl;
 
-	if ((!info.count && (info.indexed || !info.count_from_stream_output)) ||
-	    (info.indexed && !rctx->index_buffer.buffer)) {
+	if ((!info->count && (info->indexed || !info->count_from_stream_output)) ||
+	    (info->indexed && !rctx->index_buffer.buffer)) {
 		return;
 	}
 
@@ -479,50 +535,29 @@ void si_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *dinfo)
 	si_update_derived_state(rctx);
 	si_vertex_buffer_update(rctx);
 
-	rdraw.vgt_num_indices = info.count;
-	rdraw.vgt_num_instances = info.instance_count;
-
-	if (info.indexed) {
+	if (info->indexed) {
 		/* Initialize the index buffer struct. */
 		pipe_resource_reference(&ib.buffer, rctx->index_buffer.buffer);
 		ib.index_size = rctx->index_buffer.index_size;
-		ib.offset = rctx->index_buffer.offset + info.start * ib.index_size;
+		ib.offset = rctx->index_buffer.offset + info->start * ib.index_size;
 
 		/* Translate or upload, if needed. */
-		r600_translate_index_buffer(rctx, &ib, info.count);
+		r600_translate_index_buffer(rctx, &ib, info->count);
 
 		if (ib.user_buffer) {
-			r600_upload_index_buffer(rctx, &ib, info.count);
+			r600_upload_index_buffer(rctx, &ib, info->count);
 		}
 
-		/* Initialize the r600_draw struct with index buffer info. */
-		if (ib.index_size == 4) {
-			rdraw.vgt_index_type = V_028A7C_VGT_INDEX_32 |
-				(R600_BIG_ENDIAN ? V_028A7C_VGT_DMA_SWAP_32_BIT : 0);
-		} else {
-			rdraw.vgt_index_type = V_028A7C_VGT_INDEX_16 |
-				(R600_BIG_ENDIAN ? V_028A7C_VGT_DMA_SWAP_16_BIT : 0);
-		}
-		rdraw.indices = (struct si_resource*)ib.buffer;
-		rdraw.indices_bo_offset = ib.offset;
-		rdraw.vgt_draw_initiator = V_0287F0_DI_SRC_SEL_DMA;
-	} else {
-		info.index_bias = info.start;
-		rdraw.vgt_draw_initiator = V_0287F0_DI_SRC_SEL_AUTO_INDEX;
-		if (info.count_from_stream_output) {
-			rdraw.vgt_draw_initiator |= S_0287F0_USE_OPAQUE(1);
-
-			r600_context_draw_opaque_count(rctx, (struct r600_so_target*)info.count_from_stream_output);
-		}
+	} else if (info->count_from_stream_output) {
+		r600_context_draw_opaque_count(rctx, (struct r600_so_target*)info->count_from_stream_output);
 	}
 
 	rctx->vs_shader_so_strides = rctx->vs_shader->so_strides;
 
-	if (!si_update_draw_info_state(rctx, &info))
+	if (!si_update_draw_info_state(rctx, info))
 		return;
 
-	rdraw.db_render_override = dsa->db_render_override;
-	rdraw.db_render_control = dsa->db_render_control;
+	si_state_draw(rctx, info, &ib);
 
 	cp_coher_cntl = si_pm4_sync_flags(rctx);
 	if (cp_coher_cntl) {
@@ -547,7 +582,6 @@ void si_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *dinfo)
 	}
 #endif
 
-	si_context_draw(rctx, &rdraw);
 
 	rctx->flags |= R600_CONTEXT_DST_CACHES_DIRTY;