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authorMarek Olšák <[email protected]>2018-08-28 15:49:31 -0400
committerMarek Olšák <[email protected]>2018-09-10 15:19:56 -0400
commita1b9a00f82db79e59e4a743d52bb62c998584690 (patch)
tree24d500f9142fde591bb7a1aceeb07a35c75a5c17 /src/gallium/drivers/radeonsi/si_texture.c
parent5162735957555137d6620f92bcf3a9d5f54c5cd0 (diff)
radeonsi: fix HTILE for NPOT textures with mipmapping on SI/CI
VI uses addrlib so it's unaffected. Cc: 18.1 18.2 <[email protected]> Tested-by: Dieter Nützel <[email protected]>
Diffstat (limited to 'src/gallium/drivers/radeonsi/si_texture.c')
-rw-r--r--src/gallium/drivers/radeonsi/si_texture.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/src/gallium/drivers/radeonsi/si_texture.c b/src/gallium/drivers/radeonsi/si_texture.c
index e55fd815264..bcff226a586 100644
--- a/src/gallium/drivers/radeonsi/si_texture.c
+++ b/src/gallium/drivers/radeonsi/si_texture.c
@@ -931,8 +931,8 @@ static void si_texture_get_htile_size(struct si_screen *sscreen,
return;
}
- width = align(tex->buffer.b.b.width0, cl_width * 8);
- height = align(tex->buffer.b.b.height0, cl_height * 8);
+ width = align(tex->surface.u.legacy.level[0].nblk_x, cl_width * 8);
+ height = align(tex->surface.u.legacy.level[0].nblk_y, cl_height * 8);
slice_elements = (width * height) / (8 * 8);
slice_bytes = slice_elements * 4;