diff options
| author | Marek Olšák <[email protected]> | 2015-04-16 20:44:54 +0200 |
|---|---|---|
| committer | Marek Olšák <[email protected]> | 2015-08-14 15:02:29 +0200 |
| commit | 2d1952e2a5abd273983374b420371d263388bb20 (patch) | |
| tree | fe4f1c65077f969c1dc7e98b70d4ea95726eb674 /src/gallium/drivers/radeonsi/si_state_shaders.c | |
| parent | 943a4b5e963a3bbeb3a0a39d0123e359fdf3ec07 (diff) | |
radeonsi: add VI hardware support
Diffstat (limited to 'src/gallium/drivers/radeonsi/si_state_shaders.c')
| -rw-r--r-- | src/gallium/drivers/radeonsi/si_state_shaders.c | 8 |
1 files changed, 7 insertions, 1 deletions
diff --git a/src/gallium/drivers/radeonsi/si_state_shaders.c b/src/gallium/drivers/radeonsi/si_state_shaders.c index 044acd8fcea..0347014948d 100644 --- a/src/gallium/drivers/radeonsi/si_state_shaders.c +++ b/src/gallium/drivers/radeonsi/si_state_shaders.c @@ -1016,7 +1016,7 @@ bcolor: static void si_init_gs_rings(struct si_context *sctx) { unsigned esgs_ring_size = 128 * 1024; - unsigned gsvs_ring_size = 64 * 1024 * 1024; + unsigned gsvs_ring_size = 60 * 1024 * 1024; assert(!sctx->gs_rings); sctx->gs_rings = CALLOC_STRUCT(si_pm4_state); @@ -1028,6 +1028,12 @@ static void si_init_gs_rings(struct si_context *sctx) PIPE_USAGE_DEFAULT, gsvs_ring_size); if (sctx->b.chip_class >= CIK) { + if (sctx->b.chip_class >= VI) { + /* The maximum sizes are 63.999 MB on VI, because + * the register fields only have 18 bits. */ + assert(esgs_ring_size / 256 < (1 << 18)); + assert(gsvs_ring_size / 256 < (1 << 18)); + } si_pm4_set_reg(sctx->gs_rings, R_030900_VGT_ESGS_RING_SIZE, esgs_ring_size / 256); si_pm4_set_reg(sctx->gs_rings, R_030904_VGT_GSVS_RING_SIZE, |