diff options
| author | Marek Olšák <[email protected]> | 2016-06-24 02:17:38 +0200 |
|---|---|---|
| committer | Marek Olšák <[email protected]> | 2016-06-24 17:36:43 +0200 |
| commit | 28d0d0c5b4ba9e636b540fafa3b9b2157e848757 (patch) | |
| tree | 20960d753d774cdd02b35f99266eef56196619d5 /src/gallium/drivers/radeonsi/si_state_draw.c | |
| parent | 0d638f4b3d2ff9c5a00828bd3d6743d1a70cf8be (diff) | |
radeonsi: fix fractional odd tessellation spacing for Polaris
ported from Vulkan (and no source explains why this is needed)
Cc: 12.0 <[email protected]>
Reviewed-by: Nicolai Hähnle <[email protected]>
Diffstat (limited to 'src/gallium/drivers/radeonsi/si_state_draw.c')
| -rw-r--r-- | src/gallium/drivers/radeonsi/si_state_draw.c | 19 |
1 files changed, 19 insertions, 0 deletions
diff --git a/src/gallium/drivers/radeonsi/si_state_draw.c b/src/gallium/drivers/radeonsi/si_state_draw.c index 712e3df9243..717149bceb1 100644 --- a/src/gallium/drivers/radeonsi/si_state_draw.c +++ b/src/gallium/drivers/radeonsi/si_state_draw.c @@ -438,6 +438,25 @@ static void si_emit_draw_registers(struct si_context *sctx, unsigned gs_out_prim = si_conv_prim_to_gs_out(sctx->current_rast_prim); unsigned ia_multi_vgt_param, ls_hs_config, num_patches = 0; + /* Polaris needs different VTX_REUSE_DEPTH settings depending on + * whether the "fractional odd" tessellation spacing is used. + */ + if (sctx->b.family >= CHIP_POLARIS10) { + struct si_shader_selector *tes = sctx->tes_shader.cso; + unsigned vtx_reuse_depth = 30; + + if (tes && + tes->info.properties[TGSI_PROPERTY_TES_SPACING] == + PIPE_TESS_SPACING_FRACTIONAL_ODD) + vtx_reuse_depth = 14; + + if (vtx_reuse_depth != sctx->last_vtx_reuse_depth) { + radeon_set_context_reg(cs, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL, + vtx_reuse_depth); + sctx->last_vtx_reuse_depth = vtx_reuse_depth; + } + } + if (sctx->tes_shader.cso) si_emit_derived_tess_state(sctx, info, &num_patches); |