diff options
| author | Sonny Jiang <[email protected]> | 2018-10-03 11:53:12 -0400 |
|---|---|---|
| committer | Marek Olšák <[email protected]> | 2018-10-05 19:04:13 -0400 |
| commit | 4de328da079185109758d0dc1eedc60c73124273 (patch) | |
| tree | 88d260b6aaefca0e2f0d0361f94031807fcd01d3 /src/gallium/drivers/radeonsi/si_state.h | |
| parent | f243980f2c1e8005dab0cbadf52eb4392feb2ecc (diff) | |
radeonsi:optimizing SET_CONTEXT_REG for shaders PS
Signed-off-by: Sonny Jiang <[email protected]>
Signed-off-by: Marek Olšák <[email protected]>
Diffstat (limited to 'src/gallium/drivers/radeonsi/si_state.h')
| -rw-r--r-- | src/gallium/drivers/radeonsi/si_state.h | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/src/gallium/drivers/radeonsi/si_state.h b/src/gallium/drivers/radeonsi/si_state.h index bf1ae9f18f8..878b67f0ed3 100644 --- a/src/gallium/drivers/radeonsi/si_state.h +++ b/src/gallium/drivers/radeonsi/si_state.h @@ -302,6 +302,17 @@ enum si_tracked_reg { SI_TRACKED_SPI_SHADER_POS_FORMAT, SI_TRACKED_PA_CL_VTE_CNTL, + SI_TRACKED_SPI_PS_INPUT_ENA, /* 2 consecutive registers */ + SI_TRACKED_SPI_PS_INPUT_ADDR, + + SI_TRACKED_SPI_BARYC_CNTL, + SI_TRACKED_SPI_PS_IN_CONTROL, + + SI_TRACKED_SPI_SHADER_Z_FORMAT, /* 2 consecutive registers */ + SI_TRACKED_SPI_SHADER_COL_FORMAT, + + SI_TRACKED_CB_SHADER_MASK, + SI_NUM_TRACKED_REGS, }; |