radeonsi: Fix calculation of number of banks for SI

The way cik_num_banks() was calculating the index only makes sense for
the CIK specific macrotile mode array. For SI, we need to use the tile
mode index directly.

This happened to work most of the time because most of the SI tiling
modes use the same number of banks.

Reviewed-by: Marek Olšák <[email protected]>
Reviewed-by: Alex Deucher <[email protected]>

1 files changed, 14 insertions, 13 deletions

diff --git a/src/gallium/drivers/radeonsi/si_state.c b/src/gallium/drivers/radeonsi/si_state.c
index 211a6152e0c..921264e78c9 100644
--- a/src/gallium/drivers/radeonsi/si_state.c
+++ b/src/gallium/drivers/radeonsi/si_state.c
@@ -47,19 +47,19 @@ static void si_init_atom(struct r600_atom *atom, struct r600_atom **list_elem,
 	*list_elem = atom;
 }
 
-uint32_t cik_num_banks(struct si_screen *sscreen, unsigned bpe, unsigned tile_split)
+uint32_t si_num_banks(struct si_screen *sscreen, unsigned bpe, unsigned tile_split,
+		      unsigned tile_mode_index)
 {
-	unsigned index, tileb;
-
-	tileb = 8 * 8 * bpe;
-	tileb = MIN2(tile_split, tileb);
-
-	for (index = 0; tileb > 64; index++) {
-		tileb >>= 1;
-	}
-
 	if ((sscreen->b.chip_class == CIK) &&
 	    sscreen->b.info.cik_macrotile_mode_array_valid) {
+		unsigned index, tileb;
+
+		tileb = 8 * 8 * bpe;
+		tileb = MIN2(tile_split, tileb);
+
+		for (index = 0; tileb > 64; index++) {
+			tileb >>= 1;
+		}
 		assert(index < 16);
 
 		return (sscreen->b.info.cik_macrotile_mode_array[index] >> 6) & 0x3;
@@ -67,9 +67,9 @@ uint32_t cik_num_banks(struct si_screen *sscreen, unsigned bpe, unsigned tile_sp
 
 	if ((sscreen->b.chip_class == SI) &&
 	    sscreen->b.info.si_tile_mode_array_valid) {
-		assert(index < 16);
+		assert(tile_mode_index < 32);
 
-		return (sscreen->b.info.si_tile_mode_array[index] >> 20) & 0x3;
+		return (sscreen->b.info.si_tile_mode_array[tile_mode_index] >> 20) & 0x3;
 	}
 
 	/* The old way. */
@@ -1785,7 +1785,8 @@ static void si_init_depth_surface(struct si_context *sctx,
 		macro_aspect = cik_macro_tile_aspect(macro_aspect);
 		bankw = cik_bank_wh(bankw);
 		bankh = cik_bank_wh(bankh);
-		nbanks = cik_num_banks(sscreen, rtex->surface.bpe, rtex->surface.tile_split);
+		nbanks = si_num_banks(sscreen, rtex->surface.bpe, rtex->surface.tile_split,
+				      ~0);
 		tile_mode_index = si_tile_mode_index(rtex, level, false);
 		pipe_config = cik_db_pipe_config(sscreen, tile_mode_index);