diff options
| author | Marek Olšák <[email protected]> | 2018-09-28 18:49:29 -0400 |
|---|---|---|
| committer | Marek Olšák <[email protected]> | 2018-10-16 15:28:22 -0400 |
| commit | 9e182b8313c5ab952498a76495f57e8420f9e5ad (patch) | |
| tree | d365aefb270bd6cbf4dfb03b4435dba9de2a1671 /src/gallium/drivers/radeonsi/si_state.c | |
| parent | fedc1fda3096d6e41ccd40efdcff6dc966badbc3 (diff) | |
radeonsi: center viewport to improve guardband clipping for high resolutions
This will be more useful when we change the quant mode to increase subpixel
precision and decrease the viewport range (which might not be possible
if the viewport is not centered in the viewport range).
Diffstat (limited to 'src/gallium/drivers/radeonsi/si_state.c')
| -rw-r--r-- | src/gallium/drivers/radeonsi/si_state.c | 11 |
1 files changed, 9 insertions, 2 deletions
diff --git a/src/gallium/drivers/radeonsi/si_state.c b/src/gallium/drivers/radeonsi/si_state.c index a170d525ecf..babd171cbdb 100644 --- a/src/gallium/drivers/radeonsi/si_state.c +++ b/src/gallium/drivers/radeonsi/si_state.c @@ -2730,6 +2730,15 @@ static void si_set_framebuffer_state(struct pipe_context *ctx, bool unbound = false; int i; + /* Reject zero-sized framebuffers due to a hw bug on SI that occurs + * when PA_SU_HARDWARE_SCREEN_OFFSET != 0 and any_scissor.BR_X/Y <= 0. + * We could implement the full workaround here, but it's a useless case. + */ + if ((!state->width || !state->height) && (state->nr_cbufs || state->zsbuf)) { + unreachable("the framebuffer shouldn't have zero area"); + return; + } + si_update_fb_dirtiness_after_rendering(sctx); for (i = 0; i < sctx->framebuffer.state.nr_cbufs; i++) { @@ -4879,8 +4888,6 @@ static void si_init_config(struct si_context *sctx) S_028230_ER_LINE_RL(0x26) | S_028230_ER_LINE_TB(0xA) | S_028230_ER_LINE_BT(0xA)); - /* PA_SU_HARDWARE_SCREEN_OFFSET must be 0 due to hw bug on SI */ - si_pm4_set_reg(pm4, R_028234_PA_SU_HARDWARE_SCREEN_OFFSET, 0); si_pm4_set_reg(pm4, R_028820_PA_CL_NANINF_CNTL, 0); si_pm4_set_reg(pm4, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 0x0); si_pm4_set_reg(pm4, R_028AC4_DB_SRESULTS_COMPARE_STATE1, 0x0); |