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authorMarek Olšák <[email protected]>2018-10-26 22:07:29 -0400
committerMarek Olšák <[email protected]>2018-10-30 16:03:02 -0400
commit99835fff088594382884f3155ca78649156b05d1 (patch)
treed2c263b83c274b05590ce7d6179a609a8f346a75 /src/gallium/drivers/radeonsi/si_state.c
parent8ad12c8bec4bd20ea4241e412b477a155a42186b (diff)
radeonsi/gfx9: set optimal OVERWRITE_COMBINER_WATERMARK
Diffstat (limited to 'src/gallium/drivers/radeonsi/si_state.c')
-rw-r--r--src/gallium/drivers/radeonsi/si_state.c14
1 files changed, 13 insertions, 1 deletions
diff --git a/src/gallium/drivers/radeonsi/si_state.c b/src/gallium/drivers/radeonsi/si_state.c
index 36dce381539..43d76d19916 100644
--- a/src/gallium/drivers/radeonsi/si_state.c
+++ b/src/gallium/drivers/radeonsi/si_state.c
@@ -113,12 +113,13 @@ static void si_emit_cb_render_state(struct si_context *sctx)
blend &&
blend->blend_enable_4bit & cb_target_mask &&
sctx->framebuffer.nr_samples >= 2;
+ unsigned watermark = sctx->framebuffer.dcc_overwrite_combiner_watermark;
radeon_opt_set_context_reg(
sctx, R_028424_CB_DCC_CONTROL,
SI_TRACKED_CB_DCC_CONTROL,
S_028424_OVERWRITE_COMBINER_MRT_SHARING_DISABLE(1) |
- S_028424_OVERWRITE_COMBINER_WATERMARK(4) |
+ S_028424_OVERWRITE_COMBINER_WATERMARK(watermark) |
S_028424_OVERWRITE_COMBINER_DISABLE(oc_disable));
}
@@ -2855,6 +2856,7 @@ static void si_set_framebuffer_state(struct pipe_context *ctx,
sctx->framebuffer.any_dst_linear = false;
sctx->framebuffer.CB_has_shader_readable_metadata = false;
sctx->framebuffer.DB_has_shader_readable_metadata = false;
+ unsigned num_bpp64_colorbufs = 0;
for (i = 0; i < state->nr_cbufs; i++) {
if (!state->cbufs[i])
@@ -2901,6 +2903,8 @@ static void si_set_framebuffer_state(struct pipe_context *ctx,
if (tex->surface.is_linear)
sctx->framebuffer.any_dst_linear = true;
+ if (tex->surface.bpe >= 8)
+ num_bpp64_colorbufs++;
if (vi_dcc_enabled(tex, surf->base.u.tex.level))
sctx->framebuffer.CB_has_shader_readable_metadata = true;
@@ -2916,6 +2920,14 @@ static void si_set_framebuffer_state(struct pipe_context *ctx,
}
}
+ /* For optimal DCC performance. */
+ if (sctx->chip_class == VI)
+ sctx->framebuffer.dcc_overwrite_combiner_watermark = 4;
+ else if (num_bpp64_colorbufs >= 5)
+ sctx->framebuffer.dcc_overwrite_combiner_watermark = 8;
+ else
+ sctx->framebuffer.dcc_overwrite_combiner_watermark = 6;
+
struct si_texture *zstex = NULL;
if (state->zsbuf) {