diff options
| author | Marek Olšák <[email protected]> | 2016-01-30 01:27:46 +0100 |
|---|---|---|
| committer | Marek Olšák <[email protected]> | 2016-02-05 17:28:00 +0100 |
| commit | 1e864d73799cfbcb29c4f22722b908bc39643347 (patch) | |
| tree | b3f8a0eae4ee413d0f3d887ea2dad302769f74c8 /src/gallium/drivers/radeonsi/si_state.c | |
| parent | feb53912f8d8c29594a9fdff914d78bb36d6d56b (diff) | |
gallium/radeon: rename & reorder members of radeon_info
Reviewed-by: Michel Dänzer <[email protected]>
Diffstat (limited to 'src/gallium/drivers/radeonsi/si_state.c')
| -rw-r--r-- | src/gallium/drivers/radeonsi/si_state.c | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/src/gallium/drivers/radeonsi/si_state.c b/src/gallium/drivers/radeonsi/si_state.c index 7289aaad3eb..580aa789098 100644 --- a/src/gallium/drivers/radeonsi/si_state.c +++ b/src/gallium/drivers/radeonsi/si_state.c @@ -189,14 +189,14 @@ unsigned cik_db_pipe_config(struct si_screen *sscreen, unsigned tile_mode) /* This is probably broken for a lot of chips, but it's only used * if the kernel cannot return the tile mode array for CIK. */ - switch (sscreen->b.info.r600_num_tile_pipes) { + switch (sscreen->b.info.num_tile_pipes) { case 16: return V_02803C_X_ADDR_SURF_P16_32X32_16X16; case 8: return V_02803C_X_ADDR_SURF_P8_32X32_16X16; case 4: default: - if (sscreen->b.info.r600_num_backends == 4) + if (sscreen->b.info.num_render_backends == 4) return V_02803C_X_ADDR_SURF_P4_16X16; else return V_02803C_X_ADDR_SURF_P4_8X16; @@ -3572,8 +3572,8 @@ si_write_harvested_raster_configs(struct si_context *sctx, { unsigned sh_per_se = MAX2(sctx->screen->b.info.max_sh_per_se, 1); unsigned num_se = MAX2(sctx->screen->b.info.max_se, 1); - unsigned rb_mask = sctx->screen->b.info.si_backend_enabled_mask; - unsigned num_rb = MIN2(sctx->screen->b.info.r600_num_backends, 16); + unsigned rb_mask = sctx->screen->b.info.enabled_rb_mask; + unsigned num_rb = MIN2(sctx->screen->b.info.num_render_backends, 16); unsigned rb_per_pkr = MIN2(num_rb / num_se / sh_per_se, 2); unsigned rb_per_se = num_rb / num_se; unsigned se_mask[4]; @@ -3702,8 +3702,8 @@ si_write_harvested_raster_configs(struct si_context *sctx, static void si_init_config(struct si_context *sctx) { struct si_screen *sscreen = sctx->screen; - unsigned num_rb = MIN2(sctx->screen->b.info.r600_num_backends, 16); - unsigned rb_mask = sctx->screen->b.info.si_backend_enabled_mask; + unsigned num_rb = MIN2(sctx->screen->b.info.num_render_backends, 16); + unsigned rb_mask = sctx->screen->b.info.enabled_rb_mask; unsigned raster_config, raster_config_1; uint64_t border_color_va = sctx->border_color_buffer->gpu_address; struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state); |