diff options
author | Marek Olšák <[email protected]> | 2017-11-26 03:38:44 +0100 |
---|---|---|
committer | Marek Olšák <[email protected]> | 2017-11-29 18:21:30 +0100 |
commit | 950221f9231eac6e76addf5e806e45fde6e35fc0 (patch) | |
tree | 9620f5c6b20f2b58ae99902756f633e6cd7e896b /src/gallium/drivers/radeonsi/si_state.c | |
parent | 4d1fe8f9646a9ad20ba8eedd8b9deac493e69989 (diff) |
radeonsi: remove r600_common_screen
Most files in gallium/radeon now include si_pipe.h.
chip_class and family are now here:
sscreen->info.family
sscreen->info.chip_class
Reviewed-by: Nicolai Hähnle <[email protected]>
Diffstat (limited to 'src/gallium/drivers/radeonsi/si_state.c')
-rw-r--r-- | src/gallium/drivers/radeonsi/si_state.c | 92 |
1 files changed, 46 insertions, 46 deletions
diff --git a/src/gallium/drivers/radeonsi/si_state.c b/src/gallium/drivers/radeonsi/si_state.c index b68dea9271a..5c4c38368fe 100644 --- a/src/gallium/drivers/radeonsi/si_state.c +++ b/src/gallium/drivers/radeonsi/si_state.c @@ -138,7 +138,7 @@ static void si_emit_cb_render_state(struct si_context *sctx, struct r600_atom *a } /* RB+ register settings. */ - if (sctx->screen->b.rbplus_allowed) { + if (sctx->screen->rbplus_allowed) { unsigned spi_shader_col_format = sctx->ps_shader.cso ? sctx->ps_shader.current->key.part.ps.epilog.spi_shader_col_format : 0; @@ -266,7 +266,7 @@ static void si_emit_cb_render_state(struct si_context *sctx, struct r600_atom *a radeon_emit(cs, sx_ps_downconvert); /* R_028754_SX_PS_DOWNCONVERT */ radeon_emit(cs, sx_blend_opt_epsilon); /* R_028758_SX_BLEND_OPT_EPSILON */ radeon_emit(cs, sx_blend_opt_control); /* R_02875C_SX_BLEND_OPT_CONTROL */ - } else if (sctx->screen->b.has_rbplus) { + } else if (sctx->screen->has_rbplus) { radeon_set_context_reg_seq(cs, R_028754_SX_PS_DOWNCONVERT, 3); radeon_emit(cs, 0); /* R_028754_SX_PS_DOWNCONVERT */ radeon_emit(cs, 0); /* R_028758_SX_BLEND_OPT_EPSILON */ @@ -629,7 +629,7 @@ static void *si_create_blend_state_mode(struct pipe_context *ctx, color_control |= S_028808_MODE(V_028808_CB_DISABLE); } - if (sctx->screen->b.has_rbplus) { + if (sctx->screen->has_rbplus) { /* Disable RB+ blend optimizations for dual source blending. * Vulkan does this. */ @@ -677,7 +677,7 @@ static void si_bind_blend_state(struct pipe_context *ctx, void *state) old_blend->dual_src_blend != blend->dual_src_blend || (old_blend->blend_enable_4bit != blend->blend_enable_4bit && sctx->framebuffer.nr_samples >= 2 && - sctx->screen->b.dcc_msaa_allowed)) + sctx->screen->dcc_msaa_allowed)) si_mark_atom_dirty(sctx, &sctx->cb_render_state); if (!old_blend || @@ -930,7 +930,7 @@ static void *si_create_rs_state(struct pipe_context *ctx, state->poly_smooth || state->line_smooth) | S_028A48_VPORT_SCISSOR_ENABLE(1) | - S_028A48_ALTERNATE_RBS_PER_TILE(sscreen->b.chip_class >= GFX9)); + S_028A48_ALTERNATE_RBS_PER_TILE(sscreen->info.chip_class >= GFX9)); si_pm4_set_reg(pm4, R_028BE4_PA_SU_VTX_CNTL, S_028BE4_PIX_CENTER(state->half_pixel_center) | @@ -1441,8 +1441,8 @@ static void si_emit_db_render_state(struct si_context *sctx, struct r600_atom *s if (!rs || !rs->multisample_enable) db_shader_control &= C_02880C_MASK_EXPORT_ENABLE; - if (sctx->screen->b.has_rbplus && - !sctx->screen->b.rbplus_allowed) + if (sctx->screen->has_rbplus && + !sctx->screen->rbplus_allowed) db_shader_control |= S_02880C_DUAL_QUAD_DISABLE(1); radeon_set_context_reg(cs, R_02880C_DB_SHADER_CONTROL, @@ -1603,9 +1603,9 @@ static uint32_t si_translate_texformat(struct pipe_screen *screen, int first_non_void) { struct si_screen *sscreen = (struct si_screen*)screen; - bool enable_compressed_formats = (sscreen->b.info.drm_major == 2 && - sscreen->b.info.drm_minor >= 31) || - sscreen->b.info.drm_major == 3; + bool enable_compressed_formats = (sscreen->info.drm_major == 2 && + sscreen->info.drm_minor >= 31) || + sscreen->info.drm_major == 3; bool uniform = true; int i; @@ -1674,8 +1674,8 @@ static uint32_t si_translate_texformat(struct pipe_screen *screen, } if (desc->layout == UTIL_FORMAT_LAYOUT_ETC && - (sscreen->b.family == CHIP_STONEY || - sscreen->b.chip_class >= GFX9)) { + (sscreen->info.family == CHIP_STONEY || + sscreen->info.chip_class >= GFX9)) { switch (format) { case PIPE_FORMAT_ETC1_RGB8: case PIPE_FORMAT_ETC2_RGB8: @@ -1930,7 +1930,7 @@ static unsigned si_tex_dim(struct si_screen *sscreen, struct r600_texture *rtex, /* GFX9 allocates 1D textures as 2D. */ if ((res_target == PIPE_TEXTURE_1D || res_target == PIPE_TEXTURE_1D_ARRAY) && - sscreen->b.chip_class >= GFX9 && + sscreen->info.chip_class >= GFX9 && rtex->surface.u.gfx9.resource_type == RADEON_RESOURCE_2D) { if (res_target == PIPE_TEXTURE_1D) res_target = PIPE_TEXTURE_2D; @@ -2580,7 +2580,7 @@ static void si_init_depth_surface(struct si_context *sctx, surf->db_depth_info = S_02803C_ADDR5_SWIZZLE_MASK(!rtex->tc_compatible_htile); if (sctx->b.chip_class >= CIK) { - struct radeon_info *info = &sctx->screen->b.info; + struct radeon_info *info = &sctx->screen->info; unsigned index = rtex->surface.u.legacy.tiling_index[level]; unsigned stencil_index = rtex->surface.u.legacy.stencil_tiling_index[level]; unsigned macro_index = rtex->surface.u.legacy.macro_tile_index; @@ -3310,7 +3310,7 @@ static bool si_out_of_order_rasterization(struct si_context *sctx) static void si_emit_msaa_config(struct si_context *sctx, struct r600_atom *atom) { struct radeon_winsys_cs *cs = sctx->b.gfx.cs; - unsigned num_tile_pipes = sctx->screen->b.info.num_tile_pipes; + unsigned num_tile_pipes = sctx->screen->info.num_tile_pipes; /* 33% faster rendering to linear color buffers */ bool dst_is_linear = sctx->framebuffer.any_dst_linear; bool out_of_order_rast = si_out_of_order_rasterization(sctx); @@ -3437,8 +3437,8 @@ si_make_buffer_descriptor(struct si_screen *screen, struct r600_resource *buf, desc = util_format_description(format); first_non_void = util_format_get_first_non_void_channel(format); stride = desc->block.bits / 8; - num_format = si_translate_buffer_numformat(&screen->b.b, desc, first_non_void); - data_format = si_translate_buffer_dataformat(&screen->b.b, desc, first_non_void); + num_format = si_translate_buffer_numformat(&screen->b, desc, first_non_void); + data_format = si_translate_buffer_dataformat(&screen->b, desc, first_non_void); num_records = size / stride; num_records = MIN2(num_records, (buf->b.b.width0 - offset) / stride); @@ -3466,7 +3466,7 @@ si_make_buffer_descriptor(struct si_screen *screen, struct r600_resource *buf, * - For VMEM and inst.IDXEN == 0 or STRIDE == 0, it's in byte units. * - For VMEM and inst.IDXEN == 1 and STRIDE != 0, it's in units of STRIDE. */ - if (screen->b.chip_class >= GFX9) + if (screen->info.chip_class >= GFX9) /* When vindex == 0, LLVM sets IDXEN = 0, thus changing units * from STRIDE to bytes. This works around it by setting * NUM_RECORDS to at least the size of one element, so that @@ -3476,7 +3476,7 @@ si_make_buffer_descriptor(struct si_screen *screen, struct r600_resource *buf, * IDXEN is enforced? */ num_records = num_records ? MAX2(num_records, stride) : 0; - else if (screen->b.chip_class == VI) + else if (screen->info.chip_class == VI) num_records *= stride; state[4] = 0; @@ -3638,13 +3638,13 @@ si_make_texture_descriptor(struct si_screen *screen, } } - data_format = si_translate_texformat(&screen->b.b, pipe_format, desc, first_non_void); + data_format = si_translate_texformat(&screen->b, pipe_format, desc, first_non_void); if (data_format == ~0) { data_format = 0; } /* S8 with Z32 HTILE needs a special format. */ - if (screen->b.chip_class >= GFX9 && + if (screen->info.chip_class >= GFX9 && pipe_format == PIPE_FORMAT_S8_UINT && tex->tc_compatible_htile) data_format = V_008F14_IMG_DATA_FORMAT_S8_32; @@ -3652,7 +3652,7 @@ si_make_texture_descriptor(struct si_screen *screen, if (!sampler && (res->target == PIPE_TEXTURE_CUBE || res->target == PIPE_TEXTURE_CUBE_ARRAY || - (screen->b.chip_class <= VI && + (screen->info.chip_class <= VI && res->target == PIPE_TEXTURE_3D))) { /* For the purpose of shader images, treat cube maps and 3D * textures as 2D arrays. For 3D textures, the address @@ -3697,7 +3697,7 @@ si_make_texture_descriptor(struct si_screen *screen, state[6] = 0; state[7] = 0; - if (screen->b.chip_class >= GFX9) { + if (screen->info.chip_class >= GFX9) { unsigned bc_swizzle = gfx9_border_color_swizzle(desc->swizzle); /* Depth is the the last accessible layer on Gfx9. @@ -3726,7 +3726,7 @@ si_make_texture_descriptor(struct si_screen *screen, /* The last dword is unused by hw. The shader uses it to clear * bits in the first dword of sampler state. */ - if (screen->b.chip_class <= CIK && res->nr_samples <= 1) { + if (screen->info.chip_class <= CIK && res->nr_samples <= 1) { if (first_level == last_level) state[7] = C_008F30_MAX_ANISO_RATIO; else @@ -3740,7 +3740,7 @@ si_make_texture_descriptor(struct si_screen *screen, va = tex->resource.gpu_address + tex->fmask.offset; - if (screen->b.chip_class >= GFX9) { + if (screen->info.chip_class >= GFX9) { data_format = V_008F14_IMG_DATA_FORMAT_FMASK; switch (res->nr_samples) { case 2: @@ -3788,7 +3788,7 @@ si_make_texture_descriptor(struct si_screen *screen, fmask_state[6] = 0; fmask_state[7] = 0; - if (screen->b.chip_class >= GFX9) { + if (screen->info.chip_class >= GFX9) { fmask_state[3] |= S_008F1C_SW_MODE(tex->surface.u.gfx9.fmask.swizzle_mode); fmask_state[4] |= S_008F20_DEPTH(last_layer) | S_008F20_PITCH_GFX9(tex->surface.u.gfx9.fmask.epitch); @@ -4085,9 +4085,9 @@ static void *si_create_sampler_state(struct pipe_context *ctx, const struct pipe_sampler_state *state) { struct si_context *sctx = (struct si_context *)ctx; - struct r600_common_screen *rscreen = sctx->b.screen; + struct si_screen *sscreen = sctx->screen; struct si_sampler_state *rstate = CALLOC_STRUCT(si_sampler_state); - unsigned max_aniso = rscreen->force_aniso >= 0 ? rscreen->force_aniso + unsigned max_aniso = sscreen->force_aniso >= 0 ? sscreen->force_aniso : state->max_anisotropy; unsigned max_aniso_ratio = si_tex_aniso_filter(max_aniso); union pipe_color_union clamped_border_color; @@ -4248,8 +4248,8 @@ static void *si_create_vertex_elements(struct pipe_context *ctx, * chips are VI and older except Stoney (GFX8.1). */ if (data_format == V_008F0C_BUF_DATA_FORMAT_2_10_10_10 && - sscreen->b.chip_class <= VI && - sscreen->b.family != CHIP_STONEY) { + sscreen->info.chip_class <= VI && + sscreen->info.family != CHIP_STONEY) { if (num_format == V_008F0C_BUF_NUM_FORMAT_SNORM) { v->fix_fetch[i] = SI_FIX_FETCH_A2_SNORM; } else if (num_format == V_008F0C_BUF_NUM_FORMAT_SSCALED) { @@ -4475,7 +4475,7 @@ static void si_memory_barrier(struct pipe_context *ctx, unsigned flags) /* Indices are read through TC L2 since VI. * L1 isn't used. */ - if (sctx->screen->b.chip_class <= CIK) + if (sctx->screen->info.chip_class <= CIK) sctx->b.flags |= SI_CONTEXT_WRITEBACK_GLOBAL_L2; } @@ -4492,7 +4492,7 @@ static void si_memory_barrier(struct pipe_context *ctx, unsigned flags) } /* Indirect buffers use TC L2 on GFX9, but not older hw. */ - if (sctx->screen->b.chip_class <= VI && + if (sctx->screen->info.chip_class <= VI && flags & PIPE_BARRIER_INDIRECT_BUFFER) sctx->b.flags |= SI_CONTEXT_WRITEBACK_GLOBAL_L2; } @@ -4589,7 +4589,7 @@ void si_init_state_functions(struct si_context *sctx) void si_init_screen_state_functions(struct si_screen *sscreen) { - sscreen->b.b.is_format_supported = si_is_format_supported; + sscreen->b.is_format_supported = si_is_format_supported; } static void si_set_grbm_gfx_index(struct si_context *sctx, @@ -4603,7 +4603,7 @@ static void si_set_grbm_gfx_index(struct si_context *sctx, static void si_set_grbm_gfx_index_se(struct si_context *sctx, struct si_pm4_state *pm4, unsigned se) { - assert(se == ~0 || se < sctx->screen->b.info.max_se); + assert(se == ~0 || se < sctx->screen->info.max_se); si_set_grbm_gfx_index(sctx, pm4, (se == ~0 ? S_030800_SE_BROADCAST_WRITES(1) : S_030800_SE_INDEX(se)) | @@ -4617,10 +4617,10 @@ si_write_harvested_raster_configs(struct si_context *sctx, unsigned raster_config, unsigned raster_config_1) { - unsigned sh_per_se = MAX2(sctx->screen->b.info.max_sh_per_se, 1); - unsigned num_se = MAX2(sctx->screen->b.info.max_se, 1); - unsigned rb_mask = sctx->screen->b.info.enabled_rb_mask; - unsigned num_rb = MIN2(sctx->screen->b.info.num_render_backends, 16); + unsigned sh_per_se = MAX2(sctx->screen->info.max_sh_per_se, 1); + unsigned num_se = MAX2(sctx->screen->info.max_se, 1); + unsigned rb_mask = sctx->screen->info.enabled_rb_mask; + unsigned num_rb = MIN2(sctx->screen->info.num_render_backends, 16); unsigned rb_per_pkr = MIN2(num_rb / num_se / sh_per_se, 2); unsigned rb_per_se = num_rb / num_se; unsigned se_mask[4]; @@ -4739,8 +4739,8 @@ si_write_harvested_raster_configs(struct si_context *sctx, static void si_set_raster_config(struct si_context *sctx, struct si_pm4_state *pm4) { struct si_screen *sscreen = sctx->screen; - unsigned num_rb = MIN2(sctx->screen->b.info.num_render_backends, 16); - unsigned rb_mask = sctx->screen->b.info.enabled_rb_mask; + unsigned num_rb = MIN2(sctx->screen->info.num_render_backends, 16); + unsigned rb_mask = sctx->screen->info.enabled_rb_mask; unsigned raster_config, raster_config_1; switch (sctx->b.family) { @@ -4770,7 +4770,7 @@ static void si_set_raster_config(struct si_context *sctx, struct si_pm4_state *p raster_config_1 = 0x0000002e; break; case CHIP_FIJI: - if (sscreen->b.info.cik_macrotile_mode_array[0] == 0x000000e8) { + if (sscreen->info.cik_macrotile_mode_array[0] == 0x000000e8) { /* old kernels with old tiling config */ raster_config = 0x16000012; raster_config_1 = 0x0000002a; @@ -4843,7 +4843,7 @@ static void si_init_config(struct si_context *sctx) struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state); /* Only SI can disable CLEAR_STATE for now. */ - assert(has_clear_state || sscreen->b.chip_class == SI); + assert(has_clear_state || sscreen->info.chip_class == SI); if (!pm4) return; @@ -4963,9 +4963,9 @@ static void si_init_config(struct si_context *sctx) S_00B21C_CU_EN(0xffff) | S_00B21C_WAVE_LIMIT(0x3F)); /* Compute LATE_ALLOC_VS.LIMIT. */ - unsigned num_cu_per_sh = sscreen->b.info.num_good_compute_units / - (sscreen->b.info.max_se * - sscreen->b.info.max_sh_per_se); + unsigned num_cu_per_sh = sscreen->info.num_good_compute_units / + (sscreen->info.max_se * + sscreen->info.max_sh_per_se); unsigned late_alloc_limit; /* The limit is per SH. */ if (sctx->b.family == CHIP_KABINI) { @@ -5029,7 +5029,7 @@ static void si_init_config(struct si_context *sctx) RADEON_PRIO_BORDER_COLORS); if (sctx->b.chip_class >= GFX9) { - unsigned num_se = sscreen->b.info.max_se; + unsigned num_se = sscreen->info.max_se; unsigned pc_lines = 0; switch (sctx->b.family) { |