diff options
| author | Marek Olšák <[email protected]> | 2015-12-08 17:33:55 +0100 |
|---|---|---|
| committer | Marek Olšák <[email protected]> | 2015-12-11 15:25:12 +0100 |
| commit | 8ee96ce83479693ab602964e0f157a2a51677005 (patch) | |
| tree | a941e28033095598986ac5c4716fab7e182dba7b /src/gallium/drivers/radeonsi/si_state.c | |
| parent | 99e63338fb3a4d9e8fbc176ce2af331eb36a761b (diff) | |
radeonsi: re-enable Hyper-Z for stencil
Reviewed-by: Alex Deucher <[email protected]>
Diffstat (limited to 'src/gallium/drivers/radeonsi/si_state.c')
| -rw-r--r-- | src/gallium/drivers/radeonsi/si_state.c | 12 |
1 files changed, 3 insertions, 9 deletions
diff --git a/src/gallium/drivers/radeonsi/si_state.c b/src/gallium/drivers/radeonsi/si_state.c index 1cc03f75045..c2d4d44513c 100644 --- a/src/gallium/drivers/radeonsi/si_state.c +++ b/src/gallium/drivers/radeonsi/si_state.c @@ -2217,9 +2217,8 @@ static void si_init_depth_surface(struct si_context *sctx, z_info |= S_028040_TILE_SURFACE_ENABLE(1) | S_028040_ALLOW_EXPCLEAR(1); - /* Use all of the htile_buffer for depth, because we don't - * use HTILE for stencil because of FAST_STENCIL_DISABLE. */ - s_info |= S_028044_TILE_STENCIL_DISABLE(1); + if (!(rtex->surface.flags & RADEON_SURF_SBUFFER)) + s_info |= S_028044_TILE_STENCIL_DISABLE(1); uint64_t va = rtex->htile_buffer->gpu_address; db_htile_data_base = va >> 8; @@ -3583,14 +3582,9 @@ static void si_init_config(struct si_context *sctx) si_pm4_set_reg(pm4, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 0x0); si_pm4_set_reg(pm4, R_028AC4_DB_SRESULTS_COMPARE_STATE1, 0x0); si_pm4_set_reg(pm4, R_028AC8_DB_PRELOAD_CONTROL, 0x0); - - /* There is a hang if stencil is used and fast stencil is enabled - * regardless of whether HTILE is depth-only or not. - */ si_pm4_set_reg(pm4, R_02800C_DB_RENDER_OVERRIDE, S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE) | - S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE) | - S_02800C_FAST_STENCIL_DISABLE(1)); + S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE)); si_pm4_set_reg(pm4, R_028400_VGT_MAX_VTX_INDX, ~0); si_pm4_set_reg(pm4, R_028404_VGT_MIN_VTX_INDX, 0); |