diff options
| author | Christian König <[email protected]> | 2012-07-18 13:11:03 +0200 |
|---|---|---|
| committer | Christian König <[email protected]> | 2012-07-24 12:29:30 +0200 |
| commit | 840f05da6b92ba5266385836533842b9a9fc5da9 (patch) | |
| tree | f5603fa2e5cac46ec2724271b15078203bcadc74 /src/gallium/drivers/radeonsi/si_state.c | |
| parent | e4e6f954ae8c83251c39da4327c29ba12fca8236 (diff) | |
radeonsi: move init state to new handling
Signed-off-by: Christian König <[email protected]>
Diffstat (limited to 'src/gallium/drivers/radeonsi/si_state.c')
| -rw-r--r-- | src/gallium/drivers/radeonsi/si_state.c | 40 |
1 files changed, 40 insertions, 0 deletions
diff --git a/src/gallium/drivers/radeonsi/si_state.c b/src/gallium/drivers/radeonsi/si_state.c index ba8724f3de0..0c56b90c289 100644 --- a/src/gallium/drivers/radeonsi/si_state.c +++ b/src/gallium/drivers/radeonsi/si_state.c @@ -1314,6 +1314,46 @@ void si_init_state_functions(struct r600_context *rctx) rctx->context.set_framebuffer_state = si_set_framebuffer_state; } +void si_init_config(struct r600_context *rctx) +{ + struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state); + + si_pm4_set_reg(pm4, R_028A4C_PA_SC_MODE_CNTL_1, 0x0); + + si_pm4_set_reg(pm4, R_028A10_VGT_OUTPUT_PATH_CNTL, 0x0); + si_pm4_set_reg(pm4, R_028A14_VGT_HOS_CNTL, 0x0); + si_pm4_set_reg(pm4, R_028A18_VGT_HOS_MAX_TESS_LEVEL, 0x0); + si_pm4_set_reg(pm4, R_028A1C_VGT_HOS_MIN_TESS_LEVEL, 0x0); + si_pm4_set_reg(pm4, R_028A20_VGT_HOS_REUSE_DEPTH, 0x0); + si_pm4_set_reg(pm4, R_028A24_VGT_GROUP_PRIM_TYPE, 0x0); + si_pm4_set_reg(pm4, R_028A28_VGT_GROUP_FIRST_DECR, 0x0); + si_pm4_set_reg(pm4, R_028A2C_VGT_GROUP_DECR, 0x0); + si_pm4_set_reg(pm4, R_028A30_VGT_GROUP_VECT_0_CNTL, 0x0); + si_pm4_set_reg(pm4, R_028A34_VGT_GROUP_VECT_1_CNTL, 0x0); + si_pm4_set_reg(pm4, R_028A38_VGT_GROUP_VECT_0_FMT_CNTL, 0x0); + si_pm4_set_reg(pm4, R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL, 0x0); + si_pm4_set_reg(pm4, R_028A40_VGT_GS_MODE, 0x0); + si_pm4_set_reg(pm4, R_028A84_VGT_PRIMITIVEID_EN, 0x0); + si_pm4_set_reg(pm4, R_028A8C_VGT_PRIMITIVEID_RESET, 0x0); + si_pm4_set_reg(pm4, R_028B94_VGT_STRMOUT_CONFIG, 0x0); + si_pm4_set_reg(pm4, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0x0); + si_pm4_set_reg(pm4, R_028AA8_IA_MULTI_VGT_PARAM, + S_028AA8_SWITCH_ON_EOP(1) | + S_028AA8_PARTIAL_VS_WAVE_ON(1) | + S_028AA8_PRIMGROUP_SIZE(63)); + si_pm4_set_reg(pm4, R_028AB4_VGT_REUSE_OFF, 0x00000000); + si_pm4_set_reg(pm4, R_028AB8_VGT_VTX_CNT_EN, 0x0); + si_pm4_set_reg(pm4, R_008A14_PA_CL_ENHANCE, (3 << 1) | 1); + + si_pm4_set_reg(pm4, R_028B54_VGT_SHADER_STAGES_EN, 0); + si_pm4_set_reg(pm4, R_028BD4_PA_SC_CENTROID_PRIORITY_0, 0x76543210); + si_pm4_set_reg(pm4, R_028BD8_PA_SC_CENTROID_PRIORITY_1, 0xfedcba98); + + si_pm4_set_reg(pm4, R_028804_DB_EQAA, 0x110000); + + si_pm4_set_state(rctx, init, pm4); +} + static unsigned si_conv_pipe_prim(unsigned pprim) { static const unsigned prim_conv[] = { |