diff options
| author | Marek Olšák <[email protected]> | 2019-06-06 00:25:40 -0400 |
|---|---|---|
| committer | Marek Olšák <[email protected]> | 2019-07-03 15:51:13 -0400 |
| commit | 09a905d93075da9b2f46d15c9fb77040353f7f80 (patch) | |
| tree | 1e6bfa36fb2d2eca4194b602ab9db3ef802ee262 /src/gallium/drivers/radeonsi/si_state.c | |
| parent | b680f723f8c2edd3382631d3481bfcb58d2952a5 (diff) | |
radeonsi/gfx10: set cache control registers
Acked-by: Bas Nieuwenhuizen <[email protected]>
Diffstat (limited to 'src/gallium/drivers/radeonsi/si_state.c')
| -rw-r--r-- | src/gallium/drivers/radeonsi/si_state.c | 19 |
1 files changed, 19 insertions, 0 deletions
diff --git a/src/gallium/drivers/radeonsi/si_state.c b/src/gallium/drivers/radeonsi/si_state.c index 9f3e08675ac..27e42d8cef9 100644 --- a/src/gallium/drivers/radeonsi/si_state.c +++ b/src/gallium/drivers/radeonsi/si_state.c @@ -5567,6 +5567,25 @@ static void si_init_config(struct si_context *sctx) S_028C50_MAX_DEALLOCS_IN_WAVE(512)); si_pm4_set_reg(pm4, R_02835C_PA_SC_TILE_STEERING_OVERRIDE, sscreen->info.pa_sc_tile_steering_override); + + si_pm4_set_reg(pm4, R_02807C_DB_RMI_L2_CACHE_CONTROL, + S_02807C_Z_WR_POLICY(V_02807C_CACHE_STREAM_WR) | + S_02807C_S_WR_POLICY(V_02807C_CACHE_STREAM_WR) | + S_02807C_HTILE_WR_POLICY(V_02807C_CACHE_STREAM_WR) | + S_02807C_ZPCPSD_WR_POLICY(V_02807C_CACHE_STREAM_WR) | + S_02807C_Z_RD_POLICY(V_02807C_CACHE_NOA_RD) | + S_02807C_S_RD_POLICY(V_02807C_CACHE_NOA_RD) | + S_02807C_HTILE_RD_POLICY(V_02807C_CACHE_NOA_RD)); + + si_pm4_set_reg(pm4, R_028410_CB_RMI_GL2_CACHE_CONTROL, + S_028410_CMASK_WR_POLICY(V_028410_CACHE_STREAM_WR) | + S_028410_FMASK_WR_POLICY(V_028410_CACHE_STREAM_WR) | + S_028410_DCC_WR_POLICY(V_028410_CACHE_STREAM_WR) | + S_028410_COLOR_WR_POLICY(V_028410_CACHE_STREAM_WR) | + S_028410_CMASK_RD_POLICY(V_028410_CACHE_NOA_RD) | + S_028410_FMASK_RD_POLICY(V_028410_CACHE_NOA_RD) | + S_028410_DCC_RD_POLICY(V_028410_CACHE_NOA_RD) | + S_028410_COLOR_RD_POLICY(V_028410_CACHE_NOA_RD)); } if (sctx->chip_class >= GFX8) { |