diff options
| author | Marek Olšák <[email protected]> | 2015-10-22 22:48:32 +0200 |
|---|---|---|
| committer | Marek Olšák <[email protected]> | 2015-10-27 10:49:24 +0100 |
| commit | 235d38584cd47faa2837cd66ebdc770f295f47c4 (patch) | |
| tree | ece95aa2beaee083fa42bfc4fd26d2f586fe7b13 /src/gallium/drivers/radeonsi/si_state.c | |
| parent | 5bc5dca0cbcb1a13fbe9b3a33489e88531d1eb33 (diff) | |
radeonsi: properly check if DCC is enabled and allocated
Reviewed-by: Nicolai Hähnle <[email protected]>
Diffstat (limited to 'src/gallium/drivers/radeonsi/si_state.c')
| -rw-r--r-- | src/gallium/drivers/radeonsi/si_state.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/gallium/drivers/radeonsi/si_state.c b/src/gallium/drivers/radeonsi/si_state.c index c87f661f278..18b64056bc7 100644 --- a/src/gallium/drivers/radeonsi/si_state.c +++ b/src/gallium/drivers/radeonsi/si_state.c @@ -1926,7 +1926,7 @@ static void si_initialize_color_surface(struct si_context *sctx, surf->cb_color_info = color_info; surf->cb_color_attrib = color_attrib; - if (sctx->b.chip_class >= VI && rtex->surface.dcc_enabled) { + if (sctx->b.chip_class >= VI && rtex->dcc_buffer) { unsigned max_uncompressed_block_size = 2; uint64_t dcc_offset = rtex->surface.level[level].dcc_offset; @@ -2655,7 +2655,7 @@ si_create_sampler_view_custom(struct pipe_context *ctx, view->state[5] = (S_008F24_BASE_ARRAY(state->u.tex.first_layer) | S_008F24_LAST_ARRAY(last_layer)); - if (tmp->surface.dcc_enabled) { + if (tmp->dcc_buffer) { uint64_t dcc_offset = surflevel[base_level].dcc_offset; unsigned swap = r600_translate_colorswap(pipe_format); |