diff options
| author | Marek Olšák <[email protected]> | 2017-05-13 14:01:27 +0200 |
|---|---|---|
| committer | Marek Olšák <[email protected]> | 2017-05-18 22:15:02 +0200 |
| commit | 5df24c3fa627243c259f5266359098463e41d172 (patch) | |
| tree | fd74daeabf2c0e8cf83b3c4460a62860389d5bb5 /src/gallium/drivers/radeonsi/si_shader.h | |
| parent | d88ca123508ae960c47c5ba1e4ce6e2d19d6a540 (diff) | |
radeonsi: merge constant and shader buffers descriptor lists into one
Constant buffers: slot[16], .. slot[31] (ascending)
Shader buffers: slot[15], .. slot[0] (descending)
The idea is that if we have 4 constant buffers and 2 shader buffers, we only
have to upload 6 slots. That optimization is left for a later commit.
Reviewed-by: Nicolai Hähnle <[email protected]>
Diffstat (limited to 'src/gallium/drivers/radeonsi/si_shader.h')
| -rw-r--r-- | src/gallium/drivers/radeonsi/si_shader.h | 20 |
1 files changed, 7 insertions, 13 deletions
diff --git a/src/gallium/drivers/radeonsi/si_shader.h b/src/gallium/drivers/radeonsi/si_shader.h index 1627de3980b..08e809c56b7 100644 --- a/src/gallium/drivers/radeonsi/si_shader.h +++ b/src/gallium/drivers/radeonsi/si_shader.h @@ -157,14 +157,12 @@ enum { */ SI_SGPR_RW_BUFFERS, /* rings (& stream-out, VS only) */ SI_SGPR_RW_BUFFERS_HI, - SI_SGPR_CONST_BUFFERS, - SI_SGPR_CONST_BUFFERS_HI, + SI_SGPR_CONST_AND_SHADER_BUFFERS, + SI_SGPR_CONST_AND_SHADER_BUFFERS_HI, SI_SGPR_SAMPLERS, /* images & sampler states interleaved */ SI_SGPR_SAMPLERS_HI, SI_SGPR_IMAGES, SI_SGPR_IMAGES_HI, - SI_SGPR_SHADER_BUFFERS, - SI_SGPR_SHADER_BUFFERS_HI, SI_NUM_RESOURCE_SGPRS, /* all VS variants */ @@ -197,25 +195,21 @@ enum { GFX9_SGPR_TCS_OFFCHIP_ADDR_BASE64K, GFX9_SGPR_TCS_FACTOR_ADDR_BASE64K, GFX9_SGPR_unused_to_align_the_next_pointer, - GFX9_SGPR_TCS_CONST_BUFFERS, - GFX9_SGPR_TCS_CONST_BUFFERS_HI, + GFX9_SGPR_TCS_CONST_AND_SHADER_BUFFERS, + GFX9_SGPR_TCS_CONST_AND_SHADER_BUFFERS_HI, GFX9_SGPR_TCS_SAMPLERS, /* images & sampler states interleaved */ GFX9_SGPR_TCS_SAMPLERS_HI, GFX9_SGPR_TCS_IMAGES, GFX9_SGPR_TCS_IMAGES_HI, - GFX9_SGPR_TCS_SHADER_BUFFERS, - GFX9_SGPR_TCS_SHADER_BUFFERS_HI, GFX9_TCS_NUM_USER_SGPR, /* GFX9: Merged ES-GS (VS-GS or TES-GS). */ - GFX9_SGPR_GS_CONST_BUFFERS = SI_VS_NUM_USER_SGPR, - GFX9_SGPR_GS_CONST_BUFFERS_HI, + GFX9_SGPR_GS_CONST_AND_SHADER_BUFFERS = SI_VS_NUM_USER_SGPR, + GFX9_SGPR_GS_CONST_AND_SHADER_BUFFERS_HI, GFX9_SGPR_GS_SAMPLERS, GFX9_SGPR_GS_SAMPLERS_HI, GFX9_SGPR_GS_IMAGES, GFX9_SGPR_GS_IMAGES_HI, - GFX9_SGPR_GS_SHADER_BUFFERS, - GFX9_SGPR_GS_SHADER_BUFFERS_HI, GFX9_GS_NUM_USER_SGPR, /* GS limits */ @@ -229,7 +223,7 @@ enum { /* LLVM function parameter indices */ enum { - SI_NUM_RESOURCE_PARAMS = 5, + SI_NUM_RESOURCE_PARAMS = 4, /* PS only parameters */ SI_PARAM_ALPHA_REF = SI_NUM_RESOURCE_PARAMS, |