diff options
| author | Marek Olšák <[email protected]> | 2018-02-02 21:35:20 +0100 |
|---|---|---|
| committer | Marek Olšák <[email protected]> | 2018-02-24 23:08:29 +0100 |
| commit | 190e064e63e3acb603cd63488ea822605f71ac32 (patch) | |
| tree | acdbf0b651a429fda740889b818d85b19d48913c /src/gallium/drivers/radeonsi/si_shader.h | |
| parent | 1d1df76d2b3b65f18002cec1957c6115b5bd12a5 (diff) | |
radeonsi: move 2nd-shader descriptor pointers into s[0:1]
If 32-bit pointers are supported, both pointers can be moved into s[0:1]
and then ESGS has exactly the same user data SGPR declarations as VS.
If 32-bit pointers are not supported, only one pointer can be moved into
s[0:1]. In that case, the 2nd pointer is moved before TCS constants,
so that the location is the same in HS and GS.
Reviewed-by: Nicolai Hähnle <[email protected]>
Diffstat (limited to 'src/gallium/drivers/radeonsi/si_shader.h')
| -rw-r--r-- | src/gallium/drivers/radeonsi/si_shader.h | 37 |
1 files changed, 14 insertions, 23 deletions
diff --git a/src/gallium/drivers/radeonsi/si_shader.h b/src/gallium/drivers/radeonsi/si_shader.h index ef4472ba994..e0d6f701483 100644 --- a/src/gallium/drivers/radeonsi/si_shader.h +++ b/src/gallium/drivers/radeonsi/si_shader.h @@ -195,38 +195,29 @@ enum { GFX6_SGPR_TCS_FACTOR_ADDR_BASE64K, GFX6_TCS_NUM_USER_SGPR, + /* GFX9: Merged shaders. */ +#if HAVE_32BIT_POINTERS + /* 2ND_CONST_AND_SHADER_BUFFERS is set in USER_DATA_ADDR_LO (SGPR0). */ + /* 2ND_SAMPLERS_AND_IMAGES is set in USER_DATA_ADDR_HI (SGPR1). */ + GFX9_MERGED_NUM_USER_SGPR = SI_VS_NUM_USER_SGPR, +#else + /* 2ND_CONST_AND_SHADER_BUFFERS is set in USER_DATA_ADDR_LO/HI (SGPR[0:1]). */ + GFX9_SGPR_2ND_SAMPLERS_AND_IMAGES = SI_VS_NUM_USER_SGPR, + GFX9_SGPR_2ND_SAMPLERS_AND_IMAGES_HI, + GFX9_MERGED_NUM_USER_SGPR, +#endif + /* GFX9: Merged LS-HS (VS-TCS) only. */ - GFX9_SGPR_TCS_OFFCHIP_LAYOUT = SI_VS_NUM_USER_SGPR, + GFX9_SGPR_TCS_OFFCHIP_LAYOUT = GFX9_MERGED_NUM_USER_SGPR, GFX9_SGPR_TCS_OUT_OFFSETS, GFX9_SGPR_TCS_OUT_LAYOUT, GFX9_SGPR_TCS_OFFCHIP_ADDR_BASE64K, GFX9_SGPR_TCS_FACTOR_ADDR_BASE64K, -#if !HAVE_32BIT_POINTERS - GFX9_SGPR_unused_to_align_the_next_pointer, -#endif - GFX9_SGPR_TCS_CONST_AND_SHADER_BUFFERS, -#if !HAVE_32BIT_POINTERS - GFX9_SGPR_TCS_CONST_AND_SHADER_BUFFERS_HI, -#endif - GFX9_SGPR_TCS_SAMPLERS_AND_IMAGES, -#if !HAVE_32BIT_POINTERS - GFX9_SGPR_TCS_SAMPLERS_AND_IMAGES_HI, -#endif GFX9_TCS_NUM_USER_SGPR, - /* GFX9: Merged ES-GS (VS-GS or TES-GS). */ - GFX9_SGPR_GS_CONST_AND_SHADER_BUFFERS = SI_VS_NUM_USER_SGPR, -#if !HAVE_32BIT_POINTERS - GFX9_SGPR_GS_CONST_AND_SHADER_BUFFERS_HI, -#endif - GFX9_SGPR_GS_SAMPLERS_AND_IMAGES, -#if !HAVE_32BIT_POINTERS - GFX9_SGPR_GS_SAMPLERS_AND_IMAGES_HI, -#endif - GFX9_GS_NUM_USER_SGPR, - /* GS limits */ GFX6_GS_NUM_USER_SGPR = SI_NUM_RESOURCE_SGPRS, + GFX9_GS_NUM_USER_SGPR = GFX9_MERGED_NUM_USER_SGPR, SI_GSCOPY_NUM_USER_SGPR = SI_SGPR_RW_BUFFERS + (HAVE_32BIT_POINTERS ? 1 : 2), /* PS only */ |