diff options
| author | Marek Olšák <[email protected]> | 2018-01-01 21:04:22 +0100 |
|---|---|---|
| committer | Marek Olšák <[email protected]> | 2018-02-17 04:52:17 +0100 |
| commit | 931ec80eebbfd6a301a828daa0c9945f49533611 (patch) | |
| tree | a494fe03923f83d59945e681c95425965a15a549 /src/gallium/drivers/radeonsi/si_shader.h | |
| parent | 5722cd408400196eeaf02b0dba0885a536097422 (diff) | |
radeonsi: implement 32-bit pointers in user data SGPRs (v2)
User SGPRs changes:
VS: 14 -> 9
TCS: 14 -> 10
TES: 10 -> 6
GS: 8 -> 4
GSCOPY: 2 -> 1
PS: 9 -> 5
Merged VS-TCS: 24 -> 16
Merged VS-GS: 18 -> 11
Merged TES-GS: 18 -> 11
SGPRS: 2170102 -> 2158430 (-0.54 %)
VGPRS: 1645656 -> 1641516 (-0.25 %)
Spilled SGPRs: 9078 -> 8810 (-2.95 %)
Spilled VGPRs: 130 -> 114 (-12.31 %)
Scratch size: 1508 -> 1492 (-1.06 %) dwords per thread
Code Size: 52094872 -> 52692540 (1.15 %) bytes
Max Waves: 371848 -> 372723 (0.24 %)
v2: - the shader cache needs to take address32_hi into account
- set amdgpu-32bit-address-high-bits
Reviewed-by: Samuel Pitoiset <[email protected]> (v1)
Diffstat (limited to 'src/gallium/drivers/radeonsi/si_shader.h')
| -rw-r--r-- | src/gallium/drivers/radeonsi/si_shader.h | 23 |
1 files changed, 22 insertions, 1 deletions
diff --git a/src/gallium/drivers/radeonsi/si_shader.h b/src/gallium/drivers/radeonsi/si_shader.h index 3cc49caf214..ef4472ba994 100644 --- a/src/gallium/drivers/radeonsi/si_shader.h +++ b/src/gallium/drivers/radeonsi/si_shader.h @@ -136,6 +136,7 @@ #include "util/u_queue.h" #include "ac_binary.h" +#include "ac_llvm_build.h" #include "si_state.h" struct nir_shader; @@ -150,18 +151,28 @@ struct nir_shader; /* SGPR user data indices */ enum { SI_SGPR_RW_BUFFERS, /* rings (& stream-out, VS only) */ +#if !HAVE_32BIT_POINTERS SI_SGPR_RW_BUFFERS_HI, +#endif SI_SGPR_BINDLESS_SAMPLERS_AND_IMAGES, +#if !HAVE_32BIT_POINTERS SI_SGPR_BINDLESS_SAMPLERS_AND_IMAGES_HI, +#endif SI_SGPR_CONST_AND_SHADER_BUFFERS, /* or just a constant buffer 0 pointer */ +#if !HAVE_32BIT_POINTERS SI_SGPR_CONST_AND_SHADER_BUFFERS_HI, +#endif SI_SGPR_SAMPLERS_AND_IMAGES, +#if !HAVE_32BIT_POINTERS SI_SGPR_SAMPLERS_AND_IMAGES_HI, +#endif SI_NUM_RESOURCE_SGPRS, /* all VS variants */ SI_SGPR_VERTEX_BUFFERS = SI_NUM_RESOURCE_SGPRS, +#if !HAVE_32BIT_POINTERS SI_SGPR_VERTEX_BUFFERS_HI, +#endif SI_SGPR_BASE_VERTEX, SI_SGPR_START_INSTANCE, SI_SGPR_DRAWID, @@ -190,23 +201,33 @@ enum { GFX9_SGPR_TCS_OUT_LAYOUT, GFX9_SGPR_TCS_OFFCHIP_ADDR_BASE64K, GFX9_SGPR_TCS_FACTOR_ADDR_BASE64K, +#if !HAVE_32BIT_POINTERS GFX9_SGPR_unused_to_align_the_next_pointer, +#endif GFX9_SGPR_TCS_CONST_AND_SHADER_BUFFERS, +#if !HAVE_32BIT_POINTERS GFX9_SGPR_TCS_CONST_AND_SHADER_BUFFERS_HI, +#endif GFX9_SGPR_TCS_SAMPLERS_AND_IMAGES, +#if !HAVE_32BIT_POINTERS GFX9_SGPR_TCS_SAMPLERS_AND_IMAGES_HI, +#endif GFX9_TCS_NUM_USER_SGPR, /* GFX9: Merged ES-GS (VS-GS or TES-GS). */ GFX9_SGPR_GS_CONST_AND_SHADER_BUFFERS = SI_VS_NUM_USER_SGPR, +#if !HAVE_32BIT_POINTERS GFX9_SGPR_GS_CONST_AND_SHADER_BUFFERS_HI, +#endif GFX9_SGPR_GS_SAMPLERS_AND_IMAGES, +#if !HAVE_32BIT_POINTERS GFX9_SGPR_GS_SAMPLERS_AND_IMAGES_HI, +#endif GFX9_GS_NUM_USER_SGPR, /* GS limits */ GFX6_GS_NUM_USER_SGPR = SI_NUM_RESOURCE_SGPRS, - SI_GSCOPY_NUM_USER_SGPR = SI_SGPR_RW_BUFFERS_HI + 1, + SI_GSCOPY_NUM_USER_SGPR = SI_SGPR_RW_BUFFERS + (HAVE_32BIT_POINTERS ? 1 : 2), /* PS only */ SI_SGPR_ALPHA_REF = SI_NUM_RESOURCE_SGPRS, |