diff options
author | Jason Ekstrand <[email protected]> | 2016-02-09 15:30:39 -0800 |
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committer | Jason Ekstrand <[email protected]> | 2016-02-09 15:30:39 -0800 |
commit | 768bd7f272e0dfd8cc17c49750fe8aaab78bb420 (patch) | |
tree | 5d8e07b6539565cbfe9ebff5d77cde8b6a8bf566 /src/gallium/drivers/radeonsi/si_shader.h | |
parent | 4c5dcccfba3c9d0e5c7302aa797ad8d31f18cf52 (diff) | |
parent | 8b0fb1c152fe191768953aa8c77b89034a377f83 (diff) |
Merge commit '8b0fb1c152fe191768953aa8c77b89034a377f83' into vulkan
This pulls in Rob Clark's const_index changes for NIR
Diffstat (limited to 'src/gallium/drivers/radeonsi/si_shader.h')
-rw-r--r-- | src/gallium/drivers/radeonsi/si_shader.h | 58 |
1 files changed, 22 insertions, 36 deletions
diff --git a/src/gallium/drivers/radeonsi/si_shader.h b/src/gallium/drivers/radeonsi/si_shader.h index 98bdb890a45..c42c51e0455 100644 --- a/src/gallium/drivers/radeonsi/si_shader.h +++ b/src/gallium/drivers/radeonsi/si_shader.h @@ -88,7 +88,6 @@ struct radeon_shader_reloc; #define SI_SGPR_TCS_OUT_LAYOUT 9 /* TCS & TES only */ #define SI_SGPR_TCS_IN_LAYOUT 10 /* TCS only */ #define SI_SGPR_ALPHA_REF 8 /* PS only */ -#define SI_SGPR_PS_STATE_BITS 9 /* PS only */ #define SI_VS_NUM_USER_SGPR 13 /* API VS */ #define SI_ES_NUM_USER_SGPR 12 /* API VS */ @@ -97,7 +96,7 @@ struct radeon_shader_reloc; #define SI_TES_NUM_USER_SGPR 10 #define SI_GS_NUM_USER_SGPR 8 #define SI_GSCOPY_NUM_USER_SGPR 4 -#define SI_PS_NUM_USER_SGPR 10 +#define SI_PS_NUM_USER_SGPR 9 /* LLVM function parameter indices */ #define SI_PARAM_RW_BUFFERS 0 @@ -152,27 +151,23 @@ struct radeon_shader_reloc; /* PS only parameters */ #define SI_PARAM_ALPHA_REF 4 -/* Bits: - * 0: force_persample_interp - */ -#define SI_PARAM_PS_STATE_BITS 5 -#define SI_PARAM_PRIM_MASK 6 -#define SI_PARAM_PERSP_SAMPLE 7 -#define SI_PARAM_PERSP_CENTER 8 -#define SI_PARAM_PERSP_CENTROID 9 -#define SI_PARAM_PERSP_PULL_MODEL 10 -#define SI_PARAM_LINEAR_SAMPLE 11 -#define SI_PARAM_LINEAR_CENTER 12 -#define SI_PARAM_LINEAR_CENTROID 13 -#define SI_PARAM_LINE_STIPPLE_TEX 14 -#define SI_PARAM_POS_X_FLOAT 15 -#define SI_PARAM_POS_Y_FLOAT 16 -#define SI_PARAM_POS_Z_FLOAT 17 -#define SI_PARAM_POS_W_FLOAT 18 -#define SI_PARAM_FRONT_FACE 19 -#define SI_PARAM_ANCILLARY 20 -#define SI_PARAM_SAMPLE_COVERAGE 21 -#define SI_PARAM_POS_FIXED_PT 22 +#define SI_PARAM_PRIM_MASK 5 +#define SI_PARAM_PERSP_SAMPLE 6 +#define SI_PARAM_PERSP_CENTER 7 +#define SI_PARAM_PERSP_CENTROID 8 +#define SI_PARAM_PERSP_PULL_MODEL 9 +#define SI_PARAM_LINEAR_SAMPLE 10 +#define SI_PARAM_LINEAR_CENTER 11 +#define SI_PARAM_LINEAR_CENTROID 12 +#define SI_PARAM_LINE_STIPPLE_TEX 13 +#define SI_PARAM_POS_X_FLOAT 14 +#define SI_PARAM_POS_Y_FLOAT 15 +#define SI_PARAM_POS_Z_FLOAT 16 +#define SI_PARAM_POS_W_FLOAT 17 +#define SI_PARAM_FRONT_FACE 18 +#define SI_PARAM_ANCILLARY 19 +#define SI_PARAM_SAMPLE_COVERAGE 20 +#define SI_PARAM_POS_FIXED_PT 21 #define SI_NUM_PARAMS (SI_PARAM_POS_FIXED_PT + 1) @@ -193,14 +188,6 @@ struct si_shader_selector { /* PIPE_SHADER_[VERTEX|FRAGMENT|...] */ unsigned type; - /* Whether the shader has to use a conditional assignment to - * choose between weights when emulating - * pipe_rasterizer_state::force_persample_interp. - * If false, "si_emit_spi_ps_input" will take care of it instead. - */ - bool forces_persample_interp_for_persp; - bool forces_persample_interp_for_linear; - /* GS parameters. */ unsigned esgs_itemsize; unsigned gs_input_verts_per_prim; @@ -245,6 +232,7 @@ union si_shader_key { unsigned poly_stipple:1; unsigned poly_line_smoothing:1; unsigned clamp_color:1; + unsigned force_persample_interp:1; } ps; struct { unsigned instance_divisors[SI_NUM_VERTEX_BUFFERS]; @@ -272,6 +260,7 @@ struct si_shader_config { unsigned num_vgprs; unsigned lds_size; unsigned spi_ps_input_ena; + unsigned spi_ps_input_addr; unsigned float_mode; unsigned scratch_bytes_per_wave; unsigned rsrc1; @@ -290,14 +279,10 @@ struct si_shader { struct radeon_shader_binary binary; struct si_shader_config config; - unsigned nparam; unsigned vs_output_param_offset[PIPE_MAX_SHADER_OUTPUTS]; - unsigned ps_input_param_offset[PIPE_MAX_SHADER_INPUTS]; - unsigned ps_input_interpolate[PIPE_MAX_SHADER_INPUTS]; bool uses_instanceid; unsigned nr_pos_exports; unsigned nr_param_exports; - bool dx10_clamp_mode; /* convert NaNs to 0 */ }; static inline struct tgsi_shader_info *si_get_vs_info(struct si_context *sctx) @@ -343,7 +328,8 @@ int si_compile_llvm(struct si_screen *sscreen, LLVMTargetMachineRef tm, LLVMModuleRef mod, struct pipe_debug_callback *debug, - unsigned processor); + unsigned processor, + const char *name); void si_shader_destroy(struct si_shader *shader); unsigned si_shader_io_get_unique_index(unsigned semantic_name, unsigned index); int si_shader_binary_upload(struct si_screen *sscreen, struct si_shader *shader); |