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authorDave Airlie <[email protected]>2015-07-01 04:58:24 +0100
committerDave Airlie <[email protected]>2015-07-12 22:40:51 +0100
commit4cbf0a0ccf2fb4545b206066b756fd9a07acab92 (patch)
treea4890fa9bc211304fe5a301bac972838e1bfc2a2 /src/gallium/drivers/radeonsi/si_shader.c
parent8108de4774f2542a8fe65de71b82221821f73434 (diff)
radeonsi: ARB_gpu_shader_fp64 + ARB_vertex_attrib_64bit support.
This adds the translation from TGSI to AMDGPU llvm backend, for the 64-bit opcodes. The backend pretty much handles everything for us fine. There is one patch required for SI DFRAC support, that I know off. [airlied: fixed missing comma, updated relnotes] Reviewed-by: Marek Olšák <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
Diffstat (limited to 'src/gallium/drivers/radeonsi/si_shader.c')
-rw-r--r--src/gallium/drivers/radeonsi/si_shader.c31
1 files changed, 27 insertions, 4 deletions
diff --git a/src/gallium/drivers/radeonsi/si_shader.c b/src/gallium/drivers/radeonsi/si_shader.c
index 753b238e2c0..75a29aeebc9 100644
--- a/src/gallium/drivers/radeonsi/si_shader.c
+++ b/src/gallium/drivers/radeonsi/si_shader.c
@@ -703,8 +703,15 @@ static LLVMValueRef fetch_constant(
buf = reg->Register.Dimension ? reg->Dimension.Index : 0;
idx = reg->Register.Index * 4 + swizzle;
- if (!reg->Register.Indirect)
- return bitcast(bld_base, type, si_shader_ctx->constants[buf][idx]);
+ if (!reg->Register.Indirect) {
+ if (type != TGSI_TYPE_DOUBLE)
+ return bitcast(bld_base, type, si_shader_ctx->constants[buf][idx]);
+ else {
+ return radeon_llvm_emit_fetch_double(bld_base,
+ si_shader_ctx->constants[buf][idx],
+ si_shader_ctx->constants[buf][idx + 1]);
+ }
+ }
addr = si_shader_ctx->radeon_bld.soa.addr[ireg->Index][ireg->Swizzle];
addr = LLVMBuildLoad(base->gallivm->builder, addr, "load addr reg");
@@ -713,9 +720,25 @@ static LLVMValueRef fetch_constant(
lp_build_const_int32(base->gallivm, idx * 4));
result = buffer_load_const(base->gallivm->builder, si_shader_ctx->const_resource[buf],
- addr, base->elem_type);
+ addr, bld_base->base.elem_type);
+
+ if (type != TGSI_TYPE_DOUBLE)
+ result = bitcast(bld_base, type, result);
+ else {
+ LLVMValueRef addr2, result2;
+ addr2 = si_shader_ctx->radeon_bld.soa.addr[ireg->Index][ireg->Swizzle + 1];
+ addr2 = LLVMBuildLoad(base->gallivm->builder, addr2, "load addr reg2");
+ addr2 = lp_build_mul_imm(&bld_base->uint_bld, addr2, 16);
+ addr2 = lp_build_add(&bld_base->uint_bld, addr2,
+ lp_build_const_int32(base->gallivm, idx * 4));
- return bitcast(bld_base, type, result);
+ result2 = buffer_load_const(base->gallivm->builder, si_shader_ctx->const_resource[buf],
+ addr2, bld_base->base.elem_type);
+
+ result = radeon_llvm_emit_fetch_double(bld_base,
+ result, result2);
+ }
+ return result;
}
/* Initialize arguments for the shader export intrinsic */