diff options
| author | Lyude <[email protected]> | 2017-03-16 18:00:05 -0400 |
|---|---|---|
| committer | Ilia Mirkin <[email protected]> | 2017-03-31 21:41:24 -0400 |
| commit | ffe2bd676f332172a5faa053eff6460c1f184ef5 (patch) | |
| tree | 6f653bf858e92738b89c34f5c9d222a04acbe5fb /src/gallium/drivers/radeonsi/si_pipe.c | |
| parent | 54af467334db53837171701471fb7854ccdf8dd5 (diff) | |
gallium: Add a cap to check if the driver supports fill_rectangle
Changes since v1:
- Add pipe caps for etnaviv, freedreno, swr and virgl
Signed-off-by: Lyude <[email protected]>
Reviewed-by: Ilia Mirkin <[email protected]>
Diffstat (limited to 'src/gallium/drivers/radeonsi/si_pipe.c')
| -rw-r--r-- | src/gallium/drivers/radeonsi/si_pipe.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/gallium/drivers/radeonsi/si_pipe.c b/src/gallium/drivers/radeonsi/si_pipe.c index 5a4a2e276a5..ca1e99c26dd 100644 --- a/src/gallium/drivers/radeonsi/si_pipe.c +++ b/src/gallium/drivers/radeonsi/si_pipe.c @@ -492,6 +492,7 @@ static int si_get_param(struct pipe_screen* pscreen, enum pipe_cap param) case PIPE_CAP_TGSI_FS_FBFETCH: case PIPE_CAP_TGSI_MUL_ZERO_WINS: case PIPE_CAP_UMA: + case PIPE_CAP_POLYGON_MODE_FILL_RECTANGLE: return 0; case PIPE_CAP_QUERY_BUFFER_OBJECT: |