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authorMarek Olšák <[email protected]>2017-10-06 01:01:11 +0200
committerMarek Olšák <[email protected]>2017-10-09 16:20:18 +0200
commit8e969cce382951b92529ea427216a31aaa6a47fb (patch)
tree6b9d121c5f324925b1aadc9a711299b3bb82795f /src/gallium/drivers/radeonsi/si_pipe.c
parent3784ce9782b47772c950b841f8934d51a18c4b7d (diff)
radeonsi: disable primitive binning on Vega10 (v2)
Our driver implementation is known to decrease performance for some tests, but we don't know if any apps and benchmarks (e.g. those tested by Phoronix) are affected. This disables the feature just to be safe. Set this to enable partial primitive binning: R600_DEBUG=dpbb Set this to enable full primitive binning: R600_DEBUG=dpbb,dfsm v2: add new debug options Reviewed-by: Nicolai Hähnle <[email protected]>
Diffstat (limited to 'src/gallium/drivers/radeonsi/si_pipe.c')
-rw-r--r--src/gallium/drivers/radeonsi/si_pipe.c19
1 files changed, 15 insertions, 4 deletions
diff --git a/src/gallium/drivers/radeonsi/si_pipe.c b/src/gallium/drivers/radeonsi/si_pipe.c
index e98e4fef926..d0b90e732ad 100644
--- a/src/gallium/drivers/radeonsi/si_pipe.c
+++ b/src/gallium/drivers/radeonsi/si_pipe.c
@@ -1072,10 +1072,21 @@ struct pipe_screen *radeonsi_screen_create(struct radeon_winsys *ws,
sscreen->b.family <= CHIP_POLARIS12) ||
sscreen->b.family == CHIP_VEGA10 ||
sscreen->b.family == CHIP_RAVEN;
- sscreen->dpbb_allowed = sscreen->b.chip_class >= GFX9 &&
- !(sscreen->b.debug_flags & DBG(NO_DPBB));
- sscreen->dfsm_allowed = sscreen->dpbb_allowed &&
- !(sscreen->b.debug_flags & DBG(NO_DFSM));
+
+ if (sscreen->b.debug_flags & DBG(DPBB)) {
+ sscreen->dpbb_allowed = true;
+ } else {
+ /* Only enable primitive binning on Raven by default. */
+ sscreen->dpbb_allowed = sscreen->b.family == CHIP_RAVEN &&
+ !(sscreen->b.debug_flags & DBG(NO_DPBB));
+ }
+
+ if (sscreen->b.debug_flags & DBG(DFSM)) {
+ sscreen->dfsm_allowed = sscreen->dpbb_allowed;
+ } else {
+ sscreen->dfsm_allowed = sscreen->dpbb_allowed &&
+ !(sscreen->b.debug_flags & DBG(NO_DFSM));
+ }
/* While it would be nice not to have this flag, we are constrained
* by the reality that LLVM 5.0 doesn't have working VGPR indexing