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authorMarek Olšák <[email protected]>2016-11-06 20:08:24 +0100
committerMarek Olšák <[email protected]>2017-03-30 14:44:33 +0200
commit6d21fd51b6a46accb0320a8ceb52f11edc57e82b (patch)
tree206b2d35db510dac92467a4c16ff2f933dcb988d /src/gallium/drivers/radeonsi/si_pipe.c
parent2862300d9e5caeb013a456c94b1a8ec21fa894b6 (diff)
radeonsi/gfx9: disable RB+ on Vega10
Reviewed-by: Nicolai Hähnle <[email protected]>
Diffstat (limited to 'src/gallium/drivers/radeonsi/si_pipe.c')
-rw-r--r--src/gallium/drivers/radeonsi/si_pipe.c13
1 files changed, 13 insertions, 0 deletions
diff --git a/src/gallium/drivers/radeonsi/si_pipe.c b/src/gallium/drivers/radeonsi/si_pipe.c
index 7f0b4453088..8904b9df952 100644
--- a/src/gallium/drivers/radeonsi/si_pipe.c
+++ b/src/gallium/drivers/radeonsi/si_pipe.c
@@ -839,6 +839,19 @@ struct pipe_screen *radeonsi_screen_create(struct radeon_winsys *ws)
sscreen->b.has_cp_dma = true;
sscreen->b.has_streamout = true;
+
+ /* Some chips have RB+ registers, but don't support RB+. Those must
+ * always disable it.
+ */
+ if (sscreen->b.family == CHIP_STONEY ||
+ sscreen->b.chip_class >= GFX9) {
+ sscreen->b.has_rbplus = true;
+
+ sscreen->b.rbplus_allowed =
+ !(sscreen->b.debug_flags & DBG_NO_RB_PLUS) &&
+ sscreen->b.family == CHIP_STONEY;
+ }
+
(void) mtx_init(&sscreen->shader_parts_mutex, mtx_plain);
sscreen->use_monolithic_shaders =
(sscreen->b.debug_flags & DBG_MONOLITHIC_SHADERS) != 0;