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authorSamuel Pitoiset <[email protected]>2019-08-02 12:10:43 +0200
committerSamuel Pitoiset <[email protected]>2019-08-27 08:04:05 +0200
commitd62d2840c42d0eb3433c6c0c8bfe8d506c0475b9 (patch)
tree15dc1af10891dce96f59d2881de6c3e1999a8cdd /src/gallium/drivers/radeonsi/si_pipe.c
parentaf65f9431e0fea5df0957987efeb0b87cee6cadc (diff)
ac: add has_clear_state to ac_gpu_info
Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
Diffstat (limited to 'src/gallium/drivers/radeonsi/si_pipe.c')
-rw-r--r--src/gallium/drivers/radeonsi/si_pipe.c6
1 files changed, 0 insertions, 6 deletions
diff --git a/src/gallium/drivers/radeonsi/si_pipe.c b/src/gallium/drivers/radeonsi/si_pipe.c
index 475c15c54ba..21e785dd44f 100644
--- a/src/gallium/drivers/radeonsi/si_pipe.c
+++ b/src/gallium/drivers/radeonsi/si_pipe.c
@@ -1109,12 +1109,6 @@ radeonsi_screen_create_impl(struct radeon_winsys *ws,
S_0089B0_OFFCHIP_BUFFERING(max_offchip_buffers);
}
- /* The mere presense of CLEAR_STATE in the IB causes random GPU hangs
- * on GFX6. Some CLEAR_STATE cause asic hang on radeon kernel, etc.
- * SPI_VS_OUT_CONFIG. So only enable GFX7 CLEAR_STATE on amdgpu kernel. */
- sscreen->has_clear_state = sscreen->info.chip_class >= GFX7 &&
- sscreen->info.is_amdgpu;
-
sscreen->has_distributed_tess =
sscreen->info.chip_class >= GFX8 &&
sscreen->info.max_se >= 2;