diff options
| author | Marek Olšák <[email protected]> | 2017-11-07 02:01:40 +0100 |
|---|---|---|
| committer | Marek Olšák <[email protected]> | 2018-10-30 16:03:02 -0400 |
| commit | 26cb93e229e3db3850c813f5fa156303a684c880 (patch) | |
| tree | 83fe5fa35401cd9c85f437fd2435d31725fec551 /src/gallium/drivers/radeonsi/si_pipe.c | |
| parent | 0dea85928e09c01a4f5964a56d126ac43e568a2e (diff) | |
radeonsi: add support for Raven2 (v2)
v2: fix enabling primitive binning
Reviewed-by: Samuel Pitoiset <[email protected]>
Diffstat (limited to 'src/gallium/drivers/radeonsi/si_pipe.c')
| -rw-r--r-- | src/gallium/drivers/radeonsi/si_pipe.c | 10 |
1 files changed, 6 insertions, 4 deletions
diff --git a/src/gallium/drivers/radeonsi/si_pipe.c b/src/gallium/drivers/radeonsi/si_pipe.c index 6118b8076f1..490a3714836 100644 --- a/src/gallium/drivers/radeonsi/si_pipe.c +++ b/src/gallium/drivers/radeonsi/si_pipe.c @@ -1033,10 +1033,11 @@ struct pipe_screen *radeonsi_screen_create(struct radeon_winsys *ws, if (sscreen->debug_flags & DBG(DPBB)) { sscreen->dpbb_allowed = true; } else { - /* Only enable primitive binning on Raven by default. */ + /* Only enable primitive binning on APUs by default. */ /* TODO: Investigate if binning is profitable on Vega12. */ - sscreen->dpbb_allowed = sscreen->info.family == CHIP_RAVEN && - !(sscreen->debug_flags & DBG(NO_DPBB)); + sscreen->dpbb_allowed = !(sscreen->debug_flags & DBG(NO_DPBB)) && + (sscreen->info.family == CHIP_RAVEN || + sscreen->info.family == CHIP_RAVEN2); } if (sscreen->debug_flags & DBG(DFSM)) { @@ -1063,7 +1064,8 @@ struct pipe_screen *radeonsi_screen_create(struct radeon_winsys *ws, !(sscreen->debug_flags & DBG(NO_RB_PLUS)) && (sscreen->info.family == CHIP_STONEY || sscreen->info.family == CHIP_VEGA12 || - sscreen->info.family == CHIP_RAVEN); + sscreen->info.family == CHIP_RAVEN || + sscreen->info.family == CHIP_RAVEN2); } sscreen->dcc_msaa_allowed = |