diff options
| author | Nicolai Hähnle <[email protected]> | 2017-09-08 15:15:08 +0200 |
|---|---|---|
| committer | Nicolai Hähnle <[email protected]> | 2017-09-18 11:25:19 +0200 |
| commit | 8c56c45cd48e940283a8d3e951750c57694718f9 (patch) | |
| tree | 16af1e409dd10d6c248d9392d5355b532fd58c49 /src/gallium/drivers/radeonsi/si_pipe.c | |
| parent | aab134cfa57cd2f72d4234fe3f41e392e6a4f48d (diff) | |
radeonsi: add drirc option "radeonsi_assume_no_z_fights"
This option enables a performance optimization where typical non-blending
draws with depth buffer may be rasterized out-of-order (on VI+, multi-SE
chips).
This optimization can lead to incorrect results when an applications
renders multiple objects with the same Z value at the same pixel, so we
will never enable it by default. But there may be applications that could
benefit from white-listing.
Reviewed-by: Marek Olšák <[email protected]>
Tested-by: Dieter Nützel <[email protected]>
Diffstat (limited to 'src/gallium/drivers/radeonsi/si_pipe.c')
| -rw-r--r-- | src/gallium/drivers/radeonsi/si_pipe.c | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/gallium/drivers/radeonsi/si_pipe.c b/src/gallium/drivers/radeonsi/si_pipe.c index 68d63692e4f..d6de1525717 100644 --- a/src/gallium/drivers/radeonsi/si_pipe.c +++ b/src/gallium/drivers/radeonsi/si_pipe.c @@ -1048,6 +1048,8 @@ struct pipe_screen *radeonsi_screen_create(struct radeon_winsys *ws, sscreen->has_out_of_order_rast = sscreen->b.chip_class >= VI && sscreen->b.info.max_se >= 2 && !(sscreen->b.debug_flags & DBG_NO_OUT_OF_ORDER); + sscreen->assume_no_z_fights = + driQueryOptionb(config->options, "radeonsi_assume_no_z_fights"); sscreen->has_msaa_sample_loc_bug = (sscreen->b.family >= CHIP_POLARIS10 && sscreen->b.family <= CHIP_POLARIS12) || sscreen->b.family == CHIP_VEGA10 || |