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authorMarek Olšák <[email protected]>2017-03-07 02:19:47 +0100
committerMarek Olšák <[email protected]>2017-03-15 18:17:41 +0100
commit0550f3d6313a95552da0be4a52f42fb99ea2c136 (patch)
tree17a59d385b65e5f43a2cb395fad9e107461a4687 /src/gallium/drivers/radeonsi/si_pipe.c
parenta7cc9b0fcf09ba0102bddf020c258a761e304c5e (diff)
radeonsi: implement TGSI opcodes TEX_LZ and TXF_LZ
This massively decreases VGPR spilling for DiRT Showdown, because we no longer have to use v4i32 for 2D fetches when level == 0. We now use v2i32 for those cases. DiRT Showdown - Spilled VGPRs: -26 (-81%) This surprisingly doesn't have any useful effect on performance (+ 0.05%).
Diffstat (limited to 'src/gallium/drivers/radeonsi/si_pipe.c')
-rw-r--r--src/gallium/drivers/radeonsi/si_pipe.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/gallium/drivers/radeonsi/si_pipe.c b/src/gallium/drivers/radeonsi/si_pipe.c
index d78abf763a6..a9a7c8fa42d 100644
--- a/src/gallium/drivers/radeonsi/si_pipe.c
+++ b/src/gallium/drivers/radeonsi/si_pipe.c
@@ -416,6 +416,7 @@ static int si_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
case PIPE_CAP_DOUBLES:
+ case PIPE_CAP_TGSI_TEX_TXF_LZ:
return 1;
case PIPE_CAP_INT64:
@@ -482,7 +483,6 @@ static int si_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
case PIPE_CAP_TGSI_FS_FBFETCH:
case PIPE_CAP_TGSI_MUL_ZERO_WINS:
case PIPE_CAP_UMA:
- case PIPE_CAP_TGSI_TEX_TXF_LZ:
return 0;
case PIPE_CAP_QUERY_BUFFER_OBJECT: