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authorMarek Olšák <[email protected]>2018-05-02 19:39:08 -0400
committerMarek Olšák <[email protected]>2018-05-10 18:40:07 -0400
commit125adc92adce078c1a00a25735145dbfb88afc65 (patch)
treeddc54ca5b9f4b515c77f4efa560c303ff6ea4a8b /src/gallium/drivers/radeonsi/si_get.c
parent8b9694da4b5079bca76191678ad34e90651a5fca (diff)
ac/gpu_info: add has_unaligned_shader_loads
Reviewed-by: Nicolai Hähnle <[email protected]>
Diffstat (limited to 'src/gallium/drivers/radeonsi/si_get.c')
-rw-r--r--src/gallium/drivers/radeonsi/si_get.c6
1 files changed, 1 insertions, 5 deletions
diff --git a/src/gallium/drivers/radeonsi/si_get.c b/src/gallium/drivers/radeonsi/si_get.c
index 3feb1ae7823..d2bee21a1fe 100644
--- a/src/gallium/drivers/radeonsi/si_get.c
+++ b/src/gallium/drivers/radeonsi/si_get.c
@@ -226,11 +226,7 @@ static int si_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
- /* SI doesn't support unaligned loads.
- * CIK needs DRM 2.50.0 on radeon. */
- return sscreen->info.chip_class == SI ||
- (sscreen->info.drm_major == 2 &&
- sscreen->info.drm_minor < 50);
+ return !sscreen->info.has_unaligned_shader_loads;
case PIPE_CAP_SPARSE_BUFFER_PAGE_SIZE:
/* TODO: GFX9 hangs. */